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Hi <@U01819B63HP> xschem is not annotating some of...
# xschem
a
Hi @Stefan Schippers xschem is not annotating some of the iopin/opin/ipin devices on the port list. It's possible that the outdated schematic symbol that doesn't indicate those ports could be the problem?
I've removed the symbol and it worked. Is this a bug or the expected behaviour?
s
I can't replicate the problem so please explain exactly the steps you did, what schematic did you start from, if you descended into a sub schematic, and if you ran the simulation in the sub schematic or in the top level, if you are using the current revision of xschem and any other info that might help.
a
In this example, the makefile only generates the schematic netlist.If the .sym exists, it's going to mess up the port list. Maybe this problem could be related with xschem version, I'm using xschem 3.4.5 compiled less than a month ago.
xschem-extraction.zip
s
@aquiles viza thank you for the data, will look into it right away!👍
@aquiles viza Yes the behavior is deliberate (since Nov 16 2023). If a schematic has a matching symbol xschem uses the symbol as the source for the port list. This was done to make the netlisting of a given component consistent either if netlisted as a top level or as an instance in a testbench. commit a50bfb36228b85c1323c49d63b4acfdb456159cc Author: stefan schippers <stefan.schippers@gmail.com> Date: Thu Nov 16 012655 2023 +0100 when doing spice netlisting if top level has a symbol (and the symbol has i/o ports) use the symbol for printing the top level subckt port list. This ensures same port ordering when netlisting a testbench containing a component and netlisting the component itself. Tab context menu: open Symbol / open Schematic will use the search_schematic setting and search counterpart accordingly.
@aquiles viza I think I will add a netlist warning if -like in this case- schematic and symbol port lists do not match. This warning is currently missing and this is an issue.
a
So this allows the use of a testbench as a component inside another design or testbench, right?
s
@aquiles viza yes. I often do that, for example creating a schematic for an opamp, adding a code.sym with spice commands with attribute 
only_toplevel=true
, so it will be in the netlist only if the opamp is netlisted as a top level. I create a netlist for the opamp and simulate it. Then I place the opamp symbol in a testbench and write another set of spice commands in the testbench code.sym element. The opamp code.sym will not be in the netlist.
@aquiles viza latest xschem commit issues a netlisting error if top level being netlisted has an associated symbol (.sym) file, the .sym file has ports and ports do not match with schematic.
Copy code
schippes@asus:~/.xschem/xschem_library/xschem_extraction$ xschem -n -q -x resistor.sch && echo ok
pdk installation: using /home/schippes/share/pdk
180MCU_MODELS: /home/schippes/share/pdk/models/ngspice

Paths registered on xschem:
- /home/schippes/.xschem/xschem_library
- /home/schippes/.xschem/xschem_library/xschem_extraction
- /home/schippes/share/pdk/gf180mcuA/libs.tech/xschem
- /home/schippes/share/xschem/xschem_library

xschemrc:     /home/schippes/.xschem/xschem_library/xschem_extraction/xschemrc
working path: /home/schippes/.xschem/xschem_library/xschem_extraction

-- THIS DEPENDS ON THE STRUCTURE OF THE PROJECT --
The spice is generated on $module/output/extraction/test/
When doing pex simulations, use relative references from there
setup_tcp_bespice: success : listening to TCP port: 2022
Error: Symbol /home/schippes/.xschem/xschem_library/xschem_extraction/resistor.sym: schematic pin: OUT1 not in symbol
Error: Symbol /home/schippes/.xschem/xschem_library/xschem_extraction/resistor.sym: schematic pin: IN2 not in symbol
Error: Symbol /home/schippes/.xschem/xschem_library/xschem_extraction/resistor.sym: schematic pin: IN1 not in symbol
Error: Symbol /home/schippes/.xschem/xschem_library/xschem_extraction/resistor.sym: schematic pin: OUT2 not in symbol
Error: Symbol /home/schippes/.xschem/xschem_library/xschem_extraction/resistor.sym has 4 pins, its schematic has 5 pins
Error: Symbol /home/schippes/.xschem/xschem_library/xschem_extraction/resistor.sym: symbol pin: VDD not in schematic
Error: Symbol /home/schippes/.xschem/xschem_library/xschem_extraction/resistor.sym: symbol pin: OUT not in schematic
Error: Symbol /home/schippes/.xschem/xschem_library/xschem_extraction/resistor.sym: symbol pin: VSS not in schematic
-----------/home/schippes/.xschem/xschem_library/xschem_extraction/resistor.sch
-----------/home/schippes/.xschem/xschem_library/xschem_extraction/resistor.sch

schippes@asus:~/.xschem/xschem_library/xschem_extraction$
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