Hello everyone I am using google colab openlane2 to run the vhdl codes but its giving this error, previously wen I was using verilog its was working fine. So can any one please help in running vhdl codes in colab openlane 2

Can you replace

Synthesis = Step.factory.get("Yosys.Synthesis")

by

Synthesis = Step.factory.get("Yosys.VHDLSynthesis")

and see what happens

Hello @Kareem Farid Thanks for your help. I made the changes, then ran the next command, and then it got this error. Can you please go through this ? https://colab.research.google.com/drive/1x6UQhIMagbe2RJAPkVCd2x6AeiGc_DJl?usp=sharing#scrollTo=OZK-doMPIoGm

Seems like an error in the RTL itself. I don't know much about VHDL but it says

spm.vhdl:25:20: mismatching vector length; got 4, expect 5                                                                              
                           sum <= std_logic_vector(unsigned(a_reg) + unsigned(b_reg));