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Hello, I have a problem: when OpenLane tries to route every wire, it passes a macro, and it is full ...
# openlane
c
Hello, I have a problem: when OpenLane tries to route every wire, it passes a macro, and it is full of wires. As a result, it can't find a way to continue running. I'll show you a test with 1 macro component and 32 wires connected (normally I have 3 macros of this size with 400 wires for each one). Do you have any advice or tricks to avoid the wires passing inside a macro?
m
@Charly Meyer normally, macros have an associated lef file that defines blockages that prevent routing.
c
In the left figure, OpenLane traces a wire while avoiding the existing wires described in LEF files, okay. I wonder if there are means to completely avoid going inside the macro. If not, I thought to write big rectangles in the LEF file, met1, met2, and met3 (the size of the macro), to avoid any wires going there. The other solution I thought of is to manually place the components, but I can't do that 😮‍💨.
Can you help me figure out how to use macro_placement.cfg? I use: set ::env(MACRO_PLACEMENT_CGF) [glob $::env(OPENLANE_ROOT)/designs/M/macro_placement.cfg] Verilog file module M ( input in1, in2, output out1, out2 ); tt tt1 ( .in1 (in1) .out1 (out1) ); tt tt2 ( .in1 (in2) .out1 (out2) ); and I try in macro_placement.cfg tt1 300 100 N tt2 100 300 N , M.tt1 300 100 N M.tt2 100 300 N , M.tt1 tt 300 100 N M.tt2 tt 100 300 N ...
m
@Charly Meyer If you’re synthesizing module M, I think the correct format is
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tt1  300 100 N
tt2 100  300 N
You can use magic to generate a lef representation.
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lef write -hide -pinonly M.lef
The above command should create a lef file that consists of obstruction areas covering the entire macro and pins (pin definitions override obstructions).
c
Yes, normally it's supposed to work, but in my case, no. I wonder if there are other configurations or if there's something to put inside a .lef file. ?
m
@Charly Meyer are all your macro pins (except maybe power) along the perimeter of the macro? Can you open the lef file in klayout and make sure it looks ok? Can you share the exact command that you used to create the lef file? Can you also share your config.json file for openlane?
c
Thanks for your help. You can see my configuration (it's not a JSON file). My command to create a LEF file is 'lef write ~/directory/tt.lef'. I tried to use the command '-hide -pinonly', but Magic doesn't recognize them.
config.tcl
m
@Charly Meyer Does this really work? 
lef write ~/directory/tt.lef
Can you check that the 
~/directory/tt.lef
file was actually updated? If you load 
tt
in magic, does 
lef write -hide -pinonly
generate a 
tt.lef
file in the directory where you started magic?
c
tt is a gds file
before to write the lef I type property LEFclass CORE
It's probably not the best place to say this, but I have another pressing problem. My goal is to perform LVS with the GDS provided by OpenLane and the Verilog (in black box only) using the precheck. I will manually route the power supply, and I absolutely need LVS to check if it is ok.
m
You can read gds into magic and write a lef file. LVS in precheck uses the 
lvs/user_project_wrapper/lvs_config.json
file. You can abstract (black box) cells there if you need to.
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