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<!channel>: First chipalooza test chip design is ...
# chipalooza
t
<!channel>: First chipalooza test chip design is finished (pending things I might need to do to it to get it to pass the submission checks), and is publicly available at https://github.com/RTimothyEdwards/chipalooza_projects_1. There will be only one test chip on the April shuttle because that's all I have time to do, plus I managed to fit all of the designs that were ready for tapeout. For those who are interested: The test chip is designed with a central column of power pFETs originally designed by Weston Braun (and, I've noticed, adopted by a number of designers). That allows me to power each project individually. All static configuration is done through the logic analyzer, using nearly all of the 128 output bits. Dynamic digital signals are passed to the GPIO, while analog signals are passed to the analog connections of the GPIOs. For the bandgap voltage, I'm applying an off-chip voltage reference. For current supplies, I designed a tunable current bias generator; this bias generator is not to spec with the one that was a Chipalooza project, since it requires an off-chip voltage, but it should do the job. This chip design was started on Monday when I got back from the FOSSi latch-up conference, finished in time to submit yesterday evening, although I admit I was still correcting LVS errors this morning. The rendered layout is posted here.
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Large black rectangles near the projects were comment layer rectangles forming the background for labels naming each project, for quick reference. Sadly, no time for fancy artwork, just "CHIPALOOZA 2024" written in the center in small lettering.
r
Well done!
t
@Robin Tsang: You might want to take a look a the top level schematic and check how I wired up your circuits. You had a lot of test pins and I didn't have enough time to construct multiplexers to handle them all, so I skipped a few of the internal analog signals. If you think any of the signals I left unconnected is absolutely critical, please let me know.
r
Ok I’ll check it out
Looks good. Checked all the pins and didn't see anything obviously wrong to me.
b
I noticed the 
noesd
option was used for the LSXO crystal pads. I don't think this will be an issue. Just gotta remember to handle with care. 😅
t
@Brady Etz: That shouldn't be a problem. There is already ESD protection on the pads. The "noesd" is to note that there is no series resistor, and so there shouldn't be a direct path from this connection to a FET gate with no tie-down diffusion. I have connected only circuit outputs to the "noesd" pin.
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It took me two whole days to resolve various issues (mostly DRC), which was two days more than I had hoped for, but actually about what I was expecting. As there are some other groups submitting to the shuttle run who have been allowed until tomorrow morning to finish with their submissions, it's okay that I'm running two days late, and it looks like this will go to fab on schedule.
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Tomorrow (or at least sometime in the next few days) I will send out pull requests to all (or nearly all) of the projects, as I had to make a number of small corrections. Most of them were for DRC errors of the kind that only klayout checks, and one obnoxious one in particular is the MiM cap bottom plate spacing rule, which we only very recently fixed in klayout so that it reflects the way SkyWater implements the rule (which, unfortunately, is nothing like the rule is described in the documentation, which is how it managed to be wrong for so long). Other cases involved implant layers that needed some manual patching, some conflicting cell names, etc. I tried to make as few changes as needed, although in one case, a change I made was ineffectual because the error was not what I thought it was (and seems to be an integer overflow when dealing with Y coordinates near the top of the user project area; I now have a general idea of what's happening). I am also working on adding instructions to the README in the project repository detailing what all the pin connections and digital signal connections are for each project, so everybody will know how to power up, enable, and test each of the projects on the chip.
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