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When I use Opelane2, KLayout DRC is skepped becasue openlane says "KLayout DRC is not supported for...
# ieee-sscs-dc-23
j
When I use Opelane2, KLayout DRC is skepped becasue openlane says "KLayout DRC is not supported for gf180mcuD PDK" as below. After generating, I opened the result of gds in final/klayout_gds, but it has a lot of DRC errors How can I consider this error?
m
@Junbeom Park What about 
final/magic_gds
. Does that give the same drc errors in klayout?
j
@Mitch Bailey Oh! it is clean to import magic_gds file! Thank you!
👍 1
@Mitch Bailey I didn't understand fully what you said. Using the result of Openlane, I can simulate with spice netlist from openlane in Xschem. With the respect of LVS in Klayout, spice netlist from Openlane doesn't work?
Umm.. but to do LVS, blocks generated from Openlane should be ignored?
m
I haven’t tried doing digital LVS on openlane output in klayout.
Using the result of Openlane, I can simulate with spice netlist from openlane in Xschem.
What result of openlane? extracted gds? verilog? Is there a spice netlist output of openlane?
j
Layout : gds from openlane + what I drawed manually Schematic : spice from openlane + what I drawed manually but spice from openlane has black box effect
m
What directory is the spice from openlane output?
j
In case of my design : "/home/junbeom/pico/designs/openlane/dac_matrix_decoder/runs/RUN_2024-04-20_15-34-59/final/spice/dac_matrix_decoder.spice" = [RUN directory]/final/spice/[design.spice]
m
Thanks!
So the first line is something like this, right?
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* NGSPICE file created from <designname>.ext - technology: sky130A
This spice file was created from the extracted layout. So when you use this for LVS, you are essentially comparing the layout to itself.
j
Does it mean that without other circuits, the layout should compared alone with spice?
m
@Junbeom Park Sorry, I’m not sure what you’re asking. You’re doing a mixed signal, analog and digital, design, correct? The openlane output has already passed an abstract LVS - LVS at the cell level instead of the device level. Your combined layout also needs to pass LVS. These are your source netlists: A: Analog circuit spice from xschem C: Standard cell spice from pdk D: Digital circuit gate level verilog from openlane When openlane passes LVS, that is essentially saying that D: Digital circuit gate level verilog = D’: Digital extracted layout So for your top level source, you’re using A+C+D’ which is logically equivalent, but I personally feel more comfortable using pure source netlists, if possible. However, I don’t know how to read verilog netlists into klayout LVS, so your solution may be the best at this time.
@Junbeom Park The layout standard cells may be extracted with pins in a different order than the standard cells. That will cause problems when you substitute the extracted spice from openlane for the verilog in klayout. There is a way to use wrapper cells that I used to use. I try to find the script.
j
@Mitch Bailey Thank you. I'm trying to lvs only with a generated block... but not matching
m
Using klayout right?
j
yes
I modified pin configurations of stadard cells as below. and include cdl file of standard cell
If it is difficult to lvs openlane generated blocks, making lvs without them and pluging them into lvs-clean blocks can be a way
m
I’ll see if I can put a verilog -> spice conversion script together tomorrow. Can you share your 
verilog/gl/dac_matrix_decoder.v
file?
j
you mean the verilog file I used to generate this block? I'm not sure 
verilog/gl/dac_matrix_decoder.v
<-- where is this directory. but attached file is used.
dac_matrix_decoder.v
m
Not the rtl. Running openlane should have created a power gate level verilog netlist. I assumed it would be in the 
verilog/gl
directory. If not, you might be able to find it with
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find . -name dac_matrix_decoder.v
Look at the file and if its a structural netlist with power connections.
j
OMG. using above command, I can only find RTL file. Is something wrong???
m
find . -name 'dac_matrix_decoder*.v'
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