@channel we have just merged into dev branch the alpha version of the LVS rules, it is ready for testing. You can find it here: https://github.com/IHP-GmbH/IHP-Open-PDK/tree/dev/ihp-sg13g2/libs.tech/klayout/tech/lvs Any feedback is more than welcome

Please note that this still alpha and finalization will happen over the next couple of weeks.

Thanks, Amro & Krzysztof. I ran some tests today and here is my input: 1. I was able to run the provided test cases and they worked fine. 2. I then tried to LVS a standard cell and found that the LVS seems to require the "HeatTrans" layer to recognize MOS devices. The standard cells don't have that layer, but after adding it manually, the cell passed. I would like to LVS the existing standard cells without that manual step. Any thoughts? 3. Can you briefly explain what the polygons on the *.pin layers do for the LVS? I see them used in the test case. I am used to just assigning pin labels as text (using e.g. Metal1.label) and that also seems to work fine. 4. I think there is a typo in the lyp file, making the Metal1.label layer invalid (the layer should also be "marked" by default so that one can see the text origin):

<properties>
    <frame-color>#39bfff</frame-color>
    <fill-color>#39bfff</fill-color>
    <frame-brightness>0</frame-brightness>
    <fill-brightness>0</fill-brightness>
    <dither-pattern>C11</dither-pattern>
    <line-style>C2</line-style>
    <valid>false</valid>
    <visible>true</visible>
    <transparent>false</transparent>
    <width>1</width>
    <marked>false</marked>
    <animation>0</animation>
    <name>Metal1.lbl</name>
    <source>8/1</source>

Thanks Dr. @Boris Murmann

Just confirming, the pin layer is specifically required for inductor devices (ind.pin) according to the DRM, while it is not necessary for other device types.

@Amro Tork @Farag Elsayed we found a weird behavior of the LVS deck. It is related to the

lvs_options.yml

file where the configuration is stored. So if one run a testcase once the option of

netlist_simplify: true

disappear when closing klayout. Then when starting klayout once again the option is not created what results in the LVS errors.

@Krzysztof Herman Will check

@Krzysztof Herman I haven't finished my review yet.

I have fixed that, thanks for the catch @Krzysztof Herman

Thank you, everyone. Any further thoughts on the HeatTrans layer requirement? Is there a reason why active & poly does not suffice for detecting a transistor? My main issue is that many of the provided cells (digital, IO), do not consistently use that layer on transistors.

@Boris Murmann I don't know why it's required. But all the custom devices (PCell based) has this layer on the gate. @Krzysztof Herman Could you please comment on this? If you confirmed that we don't need it, then we could remove it from the recognition requirements.

OK, I think IHP will need to make that decision. Could also be an LVS option, I guess.

Would be happy to adopt any decision they reach.

@Amro Tork I think I found one more issue: The dpantenna extraction does not seem to be implemented correctly. The test case puts a piece of p+ into the substrate without an n-well (that's not a diode, just an ohmic contact). A device with the proper n-well around it does not get recognized.

This device is not completed, we're still waiting for an answer to this question. The testcase matches the current primitive cell in

sg13g2_pr.gds

Thanks @Farag Elsayed. Thanks Dr. @Boris Murmann, yes we are aware of this issue and we have informed IHP team about this in our review slides.