Hi, to generate the dnwell guard ring we use the

devices1 -> deep n-well region

magic generator. It also adds a nwell layer that covers the entire area but it adds a lot of drc errors (+2000 on magic, +6000 on klayout). Also, after manually reducing the nwell to the borders, klayout precheck detects some drc errors on the digital logic area: • hvtp.2 : min. hvtp spacing : 0.38um • nsd.2 : min. nsdm spacing, should be manually merged if less than : 0.38um • psd.2 : min. psdm spacing, should be manually merged if less than : 0.38um Those errors were inexistent before dnwell addition, so I think both are related. Does anyone has faced something like this?

@aquiles viza There were some problems reported with the magic sky130 dnwell generator when placed over existing cells. The generator would paint a nwell region and remove a region inside. painting nwell over existing devices changed the device types! There was a patch posted for the sky130 device generator, but I doubt that the gf180 device generator has been fixed. The workaround is to create the dnwell guard ring in an empty area and then move it to where it should be. Hopefully, you have a backup of the data before you drew the dnwell guard ring.

Fortunately it has a backup. I'm going to try what you suggested. Thanks David

Let me know if there are still issues.

Generating the dnwell on an empty cell works as you said, and joining that with the design layout doesn't trigger any klayout precheck drc errors. Everything seems fine on klayout.

Magic stores layers on planes as stitched shapes that don’t overlap. That’s why magic shows mosfets on a separate layer. Be careful why placing layers hierarchically. For example, deepnwell and isosubstrate can’t overlap because they are on the same plane.

We are using res_iso_pw. It contains

isosubstrate

? Tim told that this resistor shouldn't be placed on top of nwell. The restriction applies also for dnwell?

Is the res_iso_pw is in deepnwell, you shouldn’t need (can’t use) isosubstrate. Are there any other devices in the pwell region of the dnwell?

Right now I've found that the

li

routes that we use to connect the bulks on the array of ISO devices were over

diff

and sometimes it collides with

tap

. I've removed them and drc errror got fixed.