❓ Can the setup time of a flop be negative? Is the IN pin of the flop allowed to change for some time after the clock edge? 🚀 Yes it's possible. This can occur because of clock tree distribution delays inside the flop. Because of the delay in the clock path, the logic inside the flop is effectively working with a delayed version of the clock. 👉 See the image below, the clock is delayed before it reaches the internal transmission gate. The setup time in the library is still specified relative to the boundary of the flop. Relative to the clock seen at the flop boundary the setup time of the input IN is negative. 🧠The IN can change after the clock and still be able to stabilize before the clock edge as the clock takes more time to travel to the internals of the flop. 👇 Can the hold time be negative as well? If yes how? Let us know in the comments! 🎓Join STA BootCamp only 2 seats remaining on discounted price - https://api.whatsapp.com/send/?phone=919817182494&text=Hi+vlsideepdive%2C+I+have+a+query&type=phone_number&app_absent=0