https://open-source-silicon.dev
Join Slack
<@U01EK2VDMDG> <@U02HV6B4QLU> I've been attempting to run DRC on a chip top (gf180) for several days...
# klayout
g
@Amro Tork @Farag Elsayed I've been attempting to run DRC on a chip top (gf180) for several days now, but it's taking a considerable amount of time, even with the --mp=40 option (I'm running it on Google Cloud). I've observed that the "deep" mode is significantly faster than the "flat" mode. Are there any disadvantages to using the deep mode? Are all rules being checked?
a
@Gabriel Maranhão It’s recommended that you use deep mode not flat mode.
Flat mode will take significant time and not recommended except for one final run.
Also, I believe the best number of mp is around 16 or 20. Any extra CPUs would have no extra performance gain.
Flat is the exact full run. The only issue that might happen in deep mode is missing some violations due to inter-hierarchical issues due to shapes promotions or push downs. It’s kind something that happens based on how the layout is drawn. And it happens in few rare occasions. My recommendation always use deep mode most of the time, once you feel you are ready for a big run use flat. I use flat runs once a week on weekends just to make sure highlights are aligned.
BTW, keep in mind to track memory and cpu numbers.
Every mp needs 1 Cpu + enough memory to hold the chip layout in memory approximately.
👍 1
@Gabriel Maranhão I hope that helps
g
Thank you for the information! I'll switch to deep mode. The flat mode with a comprehensive set of rules (density, connectivity, antenna, BEOL, FEOL, off-grid...) is indeed time-consuming. Currently, it has been running for over 80 hours.
yes, I'm tracking the memory and cpu numbers
a
@Gabriel Maranhão How big is your design?
80 hours is too much even for flat mode
Which version of klayout are you using?
You could run all rules in deep mode as well
Run mode doesn’t set the rules to run.
You could run all rules in deep.
g
it is a chip for the #ieee-sscs-dc-23, it is 3mm by 3mm, but we are not using the hole area, but the I/Os and metal ring, and a lot of vias, I think they increase the time a lot.
Version 28.16 on a local machine, but 28.12 on GCP
a
@Gabriel Maranhão Could you send me the run logs for the 80h run?
g
$ python3 $PDK_ROOT/$PDK/libs.tech/klayout/drc/run_drc.py --path=RING_PAD_BRACOLIN.gds --variant=D --run_mode=deep --density --antenna --mp=20
This is how I run via terminal, but from local computer i can run it direct from GUI.
a
I need the run logs
The above looks great
You might need to use —split_deep with flat mode
👍 1
This would take some of the long running rules in flat and run them in deep mode to save time
👍 1
g
a
Perfect
I’ll take a look tomorrow and get back to you.
👍 1
g
This is the .gds, it is not our complete GDS, will have more blocks, but I'm already running DRC for hole chip.
RING_PAD_BRACOLIN.gds
a
How long does the deep mode takes?
g
2-4 minutes haha, that's why I did not trust it on a first moment. I was only using flat
a
That makes sense.
Perfect.
Thanks @Gabriel Maranhão
👍 1
@Farag Elsayed Here.
16 Views
Open in Slack
PreviousNext
Powered by

What is Linen?

Linen is a search-engine friendly community platform. We offer integrations with existing Slack/Discord communities and make those conversations Google-searchable.

Powered by