Hi, simulation with digital block full-parasitic extracted netlists fails. I'm using the same instructions indicated on the 3rd chipalooza presentation, but the simulation is getting stuck using T=50n, while openlane validated STA with T=4n. This happens bith discrete and continuous models.

ONES_COUNTER_pex

spice has the ports in this order

.subckt ONES_COUNTER_pex clk ones[4] ones[9] pulse ready ones[0] ones[1] ones[6] ones[3]
+ ones[8] ones[5] ones[10] rst ones[2] ones[7] VPWR VGND

While the test bench has

x0 VSS  VDD  N2_R o0 o10 o1 o2 o3 o4 o5 o6 o7 o8 o9 VDD   ready rst ONES_COUNTER_pex

It worked! Thanks David Is there a way to read a

verilog

to get port ordering? something like

readspice

or so? Maybe generate only an empty

.subckt

from the verilog file.

Sorry, no clue.

@aquiles viza: There is a tool in my

qflow

repository called

vlog2Spice

(compiled from C code) that converts verilog to SPICE. Yosys can also read verilog and output SPICE. You can't get port ordering from verilog because verilog does not require port ordering (although there is a valid SPICE-like port syntax that does require specific ordering). Most verilog is written with ports in the form

.pin_name(net_name)

so that the name of the pin in the module is always given along with the net in the parent cell connecting to it, and ports can therefore be in any order.

Eventually I will review how to fix port ordering in gds extracted without a reference spice, now I'm too busy Thanks Tim and David