I now have DRC-clean GDS as well as the .mag file, but my LVS is failing. The top-level fanout for

dvss

is much higher in the layout netlist than in the schematic netlist, which would make me think it's shorted to something. Specifically, the

avss_ip

and

avss

nets appear in the schematic, but not the layout. (

avss

doesn't appear in the schematic pin list either, but Netgen thinks the pin lists are equivalent for now, so I'm not worrying about that yet.) Is it possible the deep n-well structures aren't captured in the layout extraction? Selecting each label and tracing it in Magic seems like everything is isolated the way it should be. I'm not seeing any shapes light up that I wouldn't expect. I went through and re-enumerated my ports in Magic and Xschem to make sure those match. I'm really stumped.

Have you tried flattening your design before extracting it? Is your dvss and avss isolated? If you connect avss to the substrate, in addition to the pwell inside the nwell, they will short at top level with dvss.

I have not. Flattening the layout, you mean? I'll give it a shot.

If you consider that dvss and avss pins are shorted outside the chip, it's not a big deal. I would include a vsub or dvss pin in your analog blocks.

The devices on the

avss

and

avss_ip

domains are all parametrized transistors with guard rings. I was under the impression they connected to the p-well inside their deep n-well region. If they short to the global substrate, that's problematic.

Look at this edge of my design. It is a NMOS inside a p-well. There is a nwell guard ring and outside another guard ring with taps to substrate. All those taps are connected to different nets. If you pwell is connected to the substrate also, it will short with dvss.

I found one of the problems. At some point I had deleted the dnwell rectangle inside the

avss_ip

deep n-well. I have that net again. I'll track down the issue with

avss

, even if it means generating the n-well again.

This is a matter for the pros. I couldn't extract an isolated sub from a layout with isolated nmos devices if it inside a child subcell. It only worked for me when I extract it the cell itself alone. I have to flatten it to see the isolated substrate pin again.

@Tim Edwards Curious about your thoughts on best practices. LVS passes with uniquely matching circuits after I flatten the layout. I believe this is caused by my level shifter subcircuit that is extracting as having shorted

avss

and

dvss

. In the top-level layout, the

avss

portion is inside a deep n-well. To simulate the circuit with the parasitic-extracted netlist, the webinar instructions require flattening anyway, so this might be a moot issue. Is there anything you'd recommend I do first to correct this?

I was just having the same issue here. We managed to solve it by adding a deep n-well layer in the level shifter layout and leaving a gazillion DRC errors there. Once at the top level, the DRC errors were gone and the LVS went fine without flattening.

@Brady Etz: "*adding a deep n-well layer in the level shifter layout*" --- Yes, that's the best solution I've found. Magic extracts each cell by itself, so if multiple ground domains are the same in a subcell, then they won't get resolved by extracting the parent cell. Slipping a deep nwell under a bunch of subcells only works if the subcells have a simple, single ground domain.