Minor hiccup with `cace`: If I'm crazy enough to w...
# chipalooza
c
Minor hiccup with `cace`: If I'm crazy enough to want to run
cace-gui -t
, cace barfs at me:
Copy code
Process Process-1:
Traceback (most recent call last):
  File "/usr/lib/python3.8/multiprocessing/process.py", line 315, in _bootstrap
    self.run()
  File "/usr/lib/python3.8/multiprocessing/process.py", line 108, in run
    self._target(*self._args, **self._kwargs)
  File "/home/cmaier/.local/lib/python3.8/site-packages/cace/cace_gui.py", line 939, in cace_process
    sys.stdout = self.stdout
AttributeError: 'CACECharacterize' object has no attribute 'stdout'
This isn't anywhere near a time-critical chokepoint at the moment, but should maybe get fixed nonetheless.
😂 3
👍 1
🟢 1
t
Okay, I can confirm that the same thing happens to me. I don't think the "-t" option was thoroughly tested at the time the last main branch was committed. The latest code (which is only in a pull request at the moment) has it fixed. Options: (1) Don't use the "-t" option. (2) Fix the problem in the CACE source, which is to change
cace/cace_gui.py
lines 939 and following from:
Copy code
sys.stdout = self.stdout
            sys.stderr = self.stderr
to
Copy code
try:
            sys.stdout = self.stdout
            sys.stderr = self.stderr
        except:
            pass
Output logging in CACE definitely needs some work.
If the April 24 chipIgnite deadline whooshes by, then I miss the train. Nevertheless, if you can get the layout done within a few days but can get me a rough layout area estimate by the end of day today, I can work with that.
c
Fair enough. Will do, and may plan for more standard high voltage digital standard cell tiles than necessary. Power supplies as per standard cell routing conventions.
With sky130 device models in ngspice throwing unexpected curveballs at me (unphysical forward biased behavior of a solidly reverse biased substrate-to-drain junction) that will need in-depth investigation, and in general the urgent need to debug a so far rather shaky IC design tool chain, while the alleged goals are to meet specifications and deadlines, I'll chase a different deadline: I need to return a book to the public library on the 17th, so I'll take the time to read Teresa Bücker: Alle Zeit — Eine Frage von Macht und Freiheit (All the Time — A Quesiton of Power and Freedom) and resume pursuing the analog chip design for fun pastime afterwards — my toy train is on the table next to the computer, and the next tapeout is lined up already, after all.
l
"So long, and thanks for all the fish". MacDolphin, Orca "Killer Whale".
c
@Luis Henrique Rodovalho, be careful what you ask for … Without reliable equipment, i.e., a solid tool chain, verified before you chase arbitrary and capricious specifications and deadlines, a

human wave

frontal assault

is proper, if desperate and extremely wasteful, management strategy, but in order to have an impact, you need time to line up an attack with _*fish*_ (i.e. torpedos). What's All That Ordem e Progresso Stuff About, Anyhow?
l
Brazilian motto is not "Ordem e Progresso". It is "É proibido, mas se quiser pode". I work at Synopsys, and I can tell you for sure. Don't look at the restaurant's kitchen, into a woman's past, or into an EDA software company's internal code. No design flow is perfect. The database is dark and full of terrors.
c
Se eu quero ou não, depende da taxa de perda dos soldados de infantaria: chipalooza 2024: 23/31 = 74% Se essa taxa de perda fosse 22/31, não faria nenhuma diferença. Limpar o código da EDA faria a diferença, e se ninguém me negar todo o financiamento para isso, fará a diferença.
l
"Nasci pelado, pobre e sem dente. O que vier é lucro". A 74% casuality rate? It's a zerg rush. It's still a profit. We are an army of south americans and south asians. A 300 USD tiny tapeout is the minimum monthly age in Brazil, but it can be the first silicon a graduate student can get in there. Efabless can give one for free. All you need to do is to learn to use a layout tool whose license server doesn't go down the day before the deadline. My Portuguese intern here is designing a TDC for his masters using 12 nm finFET because it's the oldest technology available. And he won't be able to upload his circuits to github in the end.
c
Yep, I see the potential, and I see the potential for improvement, from my position of privilege. Might as well make good use of it, and let a deadline whoosh by to make a point. Gotta pick your hill to die on … or the hill picks you, as it were.
l
For context, my first contact with microelectronics was in my engineering undergraduate course in Belém, Brazil, 2009. We made everything in microwind. Even when I was studying for my Ph.D. degree, in 2018, I was in Argentina and used LTspice with MOSFET models found on the loose in the interwebz, because there we didn't have Cadence licenses at the time. Argentina's economy is a rollercoaster... Then I had access to proprietary software made free by some Iranians, but it ran as slideshow in my laptop. Magic and ngspice can run in my potato computer! I can even fabricate real silicon with them! Of course, the RCC sims won't be finished when the design review deadline is over. Who cares!? My opamp is beautiful, real or not!
t
@Luis Henrique Rodovalho: In my opinion, it's only beautiful when it's etched in silicon. : )
c
A Hogervorst, … and Huijsing class AB amplifier, whether its layout looks like FinFET or more conventional, is extremely useful if you need to get some analog signal off chip. Been there, done that: https://bitbucket.org/cmucsd/lifeincircuits/downloads/life.pdf , slide 22 (with Easter egg video). in Gert's lab, slide 23 (with Easter egg video).
l
Still too much common sense, @Christoph Maier. Everybody teaches how to design a two stage Miller opamp or single stage folded cascode but nobody learns how to remake Huijsing class AB. Even Huijsing doesn't instruct about layout techniques or spice testbenches because it's too trivial. Now I have new hires here that never touched a layout in their lives, and paid layouters that don't know about transistor abutment. And some of them were born after 2000. I'm too old for this shit and I'm only 38. Now, get off my lawn!
c
@Luis Henrique Rodovalho, assume, hypothetically, that Cory Doctorow is correct about chokepoints and all that. What would the next Human Wave frontal assault with obscenely high casualty rates among the peasants look like, and what would be the inadequate-by-design design tool the assault would be based on?
l
Most under-developed and developing countries didn't have landlines. After the popularization of wireless communications, most skipped landlines and went directly to wireless. Some developed countries had good landline coverage, but are struggling with high speed internet because they already have a huge structure. I think the solution is automatic analog layout design, so the circuit designer shouldn't worry about it. Custom layout design should be done just for really critical circuits. Magic seems to be outdated, but its innards are really open and transparent. Someone can script it easily to make whole basic analog cells in TCL. I just don't do it myself because I want money and I'll sell my services to Synopsys, so maybe, someday I can buy my own home instead of paying half of my salary in rent.