Running into time-step too small issues running full RCX simulations. Already played around with reltol, abstol and vtol params to no avail. It’s better with relaxed tolerances but still locks up. exteresist added about 18,000 nodes to my circuit. Before extraction my spice net list was about 1,200 lines, afterwards it’s about 24,000. Any suggestions? Already simplified the circuit by black boxing the digital route, and was not included in the extraction process.

Have you tried

.option KLU

? I'm not sure if it helps but maybe give it a try.

Just tried

.option KLU

, makes no observable difference. Thank you for the suggestion.

Nice! May I ask if you have diodes in your layout? I had to use

ngspice

models to make the simulation work with them, but the results I'm getting are a complete mess.

No, the only diodes I'm using are parasitic diodes for antenna rules. You may want to check the ports to see if they are the same for

ngspice

models and

combined

models. There may be an extra substrate connection which can really throw things off. I ran into it when swithing to

combined

models for pnp. The pnp in

combined

models have an extra substrate connection and the xschem symbol in the pdk doesn't netlist out that extra substrate node. I had to create my own pnp symbol to properly get it netlisted so it works with

combined

.

Thank you for the help. I'll take a look at that.

Another thing I would do, if the rest of the circuit works well with

combined

except the diodes, I would switch out the

combined

models just for the diodes for

ngspice

models. Good luck.

Thank you @Robin Tsang. I've just commented out the diodes from the extracted netlist and ran the testbench again using

combined

models. Actually, my entire extracted circuit is a mess 😅. They were just antenna diodes, so they weren't supposed to interfere with the circuit operation. Well, it seems I'll have to dig deeper. The layout is LVS and DRC clean, but I'm getting almost a 50% variation from the schematic simulation (without parasitics).

What circuit are you making?

My friend and I are working on the overvoltage detector circuit. We are rookie designers and we are struggling a bit with this layout/post-layout phase.

I’m making the same circuit. It’s going to be hard to debug the rcx circuit since it’s been flattened. Maybe you can try the simplist extraction first, which is just extracting cap to substrate. If that works, add coupling caps, and if that works, then extract resistance.

Thank you for all the help @Robin Tsang. I'll follow these debug steps you mentioned.