<!channel>: The time has come again to post a reminder that the layout deadline is approaching! Per the usual handling of deadlines, layout should be completed and pushed to the repository by midnight Pacific Daylight Time (PDT, or GMT-7) at the end of Monday, April 15. As was done with the schematics and simulations, there will be post-layout design reviews in the days following the deadline. Additional updates can be posted up to the time of the design review. However, please note that I have to plan out the test chips for the April 24 shuttle run, and so the earlier I can get something that looks like the final layout, the better. I will send emails directly to the designers and design teams today with the link to sign up for design reviews. For expediency, only those teams or designers that had an acceptable schematic and simulation results by the time of the first design review or by the follow-up review and were given the green light for going ahead with layout will be asked to sign up for post-layout design reviews. This will allow us to give each design at least a full hour for review. If you do not receive an email about post-layout design reviews today but you believe that you will have a completed layout by the end of Monday, please let me know.