Hi @Tim Edwards @Andrew Wright we have a first iteration of the digital section in the temperatura sensor (please ignore the notes). We still have some questions about the scope of our project. - What's the maximum freq of the system clock we can obtain on chip? - If we implement the APB/Wishbone interface, do you have any advice on how to bring this out of the chip? Thanks for the advice during the system design.

@aquiles viza: We don't want the bus interface inside the design if possible. The reason is that we're developing a system that can automatically generate a bus interface to a block, for any bus type that it knows about. You probably need the bus interface for testing, so create a wrapper level for your block and define the bus interface inside that. I don't think we are at the point of defining the clock frequency for the CPU. So far, I have not seen openlane able to synthesize an SoC-scale design to more than 40MHz, so I would take that as a practical upper limit.