@Himanshu Singh, I've learned how to make layouts using logic gates by learning the full automatic logic and physical synthesis flow from cadence tools. Later, I've just copied it in my custom made layout. Even my analog layouts follow digital layouts guidelines.

re: Even my analog layouts follow digital layouts guidelines. Did you document your analog and layout guidelines (i.e., cell unit heights and widths, power, ground and maybe bias bus layout, routing grids) somewhere for the bias circuit[s] you just got back on silicon, and where would I find them?

@Christoph Maier I barely document my work even when they pay me, and I don't see any layout design papers in IEEE journals. Layout isn't sexy. But the the main idea is to use series and parallel transistor arrays and a grid, where the metal tracks obey rigid and predictable rules. • All PMOS and NMOS transistors should have the same length. • All transistors of the same kind should have the same width. • There is a horizontal bus with every signal used in the block, shielded by ground or power signals. • The diffusions (drain/source) should be routed vertically in a low level metal. • The gates should be routed vertically in the highest metal layer, to avoid antenna effects. • Power and ground planes should be routed horizontally above the transistors for easy access and shielding. See this small OTA using 0.5 um grid in sky130, as an example. Unfortunately, this design wastes too much space with the signal bus. My newer designs route the signals above the transistors too.