HI @Tim Edwards, I have designed my layout using magic and the DRC was clean. While running local precheck I got a fail for

klayout FEOL

. To see the issue I ran the DRC in klayout and I got a lot of

m1.3ab

(m1.3ab : min. 3um.m1 spacing m1 : 0.28um)

violations. I am unable to figure out what are these violations and why does magic not catch it. I need to tapeout by 24th april. Please help me with the issues.

@naina singhal this is a wide metal spacing rule. For met1 wider than 3um, the spacing to other met1 needs to be 0.28um or more. One solution is to add 0.28um slits to the wide metal. Another solution is to move the wide metal back a bit.

I think this is a false positive error in klayout caused by a bad rule implementation. If it were a real wide-spacing rule, magic would have caught it.

@Tim Edwards @Mitch Bailey The errors are present for same nets. I am using 20um long transistors and connecting both sides of gate is giving the error.

> I think this is a false positive error in klayout caused by a bad rule implementation. If it were a real wide-spacing rule, magic would have caught it. @Tim Edwards I think you’re right. looks like the metal is divided into wide and thin and the error is occurring where they touch. The rule should probably allow abutting. @Amro Tork

@naina singhal Is that GF180MCU or Skywaters?

@Amro Tork skywater.

@Mitch Bailey We don't support it.

@Amro Tork sorry for the false tag then. Hope things are well with you. Is the “don’t support” a “don’t and never did” or a “used to but not any more”?🙂

@Mitch Bailey We used to, but it's not part of our deliverables.

@Mitch Bailey @Tim Edwards is there any update regarding m1.3ab drc errors? Should I treat them as false positive only? But then the precheck is failing due to klayout FEOL.

@naina singhal: For now, treat them as false positives. If you can give us a test case, we can work on fixing the rule definition.

@Tim Edwards Please find the attached gds for test case. We need to tapeout our design on chipignite shuttle on 24 April. Please help us fixing this issue before then. One more thing, the LVS in the precheck is failing with the same errors of PNP transistor "m" property mismatch and dummy device merging issue which you fixed. @Mitch Bailey told me that netgen needs to be updated in the precheck.

@naina singhal: This is a false positive error that is resolved by an update to the klayout DRC deck that is currently pending a merge to the repository. The new deck can be found in the

mpw_precheck

repository in the branch "klayout_deck_update". This has been approved for merging but I'm not certain when it will be merged. . . I'm asking for it.

@Tim Edwards thank you so much for resolving the issue so fast. 🙂