I think @Christoph Maier was talking about latchup rules. They are checked alongside antenna rules in some flows. Some rules for transistors inside deep n wells can be nasty. I have a question, @Tim Edwards. Should the substrate, outside the nwell, be connected to dvss? Where? Won't it cause shorts to other supply pins?

Yes to all questions. Currently there is an irritating issue with the caravel user projects in that the SoC's digital ground is the effective substrate under the entire user area, except that the SoC's

vssd

domain does not actually connect (by pin) to the user project. Mitch Bailey has been working up a solution drawing isolated substrate cuts around the user area; with this solution, you can assume any ground domain you want for the substrate as long as you're consistent. ("isosub" is the layer name in magic that generates a virtual isolated substrate area or "subcut").

vssd1

is probably the most obvious choice for the user area substrate. Within the padframe, the

vssa

domains are all properly isolated with deep nwells. However, there is no specific isolation between any

vssd

domain and the

vssio

domain other than virtual isolation created by subcuts.