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I'm hitting an issue when adding the extracted layout simulation to xschem
# xschem
m
I'm hitting an issue when adding the extracted layout simulation to xschem
repo:
image.png
netlist generates ok
opamp_tb.spice
opamp_tb.spice
but spice has an error due to repeated resistors
image.png
I've done this a few times before and never hit this issue - any thoughts?
s
the 
/tmp/tt06-fet-opamp/mag/opamp.sim.spice
netlist is not wrapped inside a 
.subckt
/ 
.ends
container, so the netlist is included as top level and there are devices with clashing names (x1) The 
opamp.sim.spice
file should have a 
.subckt opamp_parax VDD ZREF vin_n vin_p Vout VGND
 line and a closing 
.ends
line
I think adding this: 
spice_sym_def=tcleval("
 
.subckt opamp_parax VDD ZREF vin_n vin_p Vout VGND
 
.include [file normalize ../mag/opamp.sim.spice]
 
.ends)"
 will solve the issue
m
ahh
thanks Stefan!
funny that it worked before
s
may be there is some option in the extraction to add the .subckt /.ends lines? @Tim Edwards
m
s
Ah, this makes all my assumptions wrong.. will check the file...
will clone the repo and test...
@Matt Venn the opamp_parax symbol instance lack a name=... attribute. Add 
name=x2
and you will be ok. since there is no name attribute it will get the default name=x1, but there is already a name=x1 in the design (the opamp symbol).
m
aha!
s
1.png
m
yes, confirmed that was the issue and now it works
that was a mistake my end
s
May be it would be nice to raise a warning in these cases, since tracking the error from ngspice error messages is not easy 😄
m
that would be nice
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