open-source-silicon.dev

I'm hitting an issue when adding the extracted layout simulation to xschem

<https://github.com/mattvenn/tt06-fet-opamp>

image.png

opamp_tb.spice

but spice has an error due to repeated resistors

I've done this a few times before and never hit this issue - any thoughts?

~the `/tmp/tt06-fet-opamp/mag/opamp.sim.spice` netlist is not wrapped inside a `.subckt` / `.ends` container, so the netlist is included as top level and there are devices with clashing names (x1)~
~The `opamp.sim.spice` file should have a~
~`.subckt opamp_parax VDD ZREF vin_n vin_p Vout VGND`~
~line and a closing `.ends` line~

~I think adding this:~
~`spice_sym_def=tcleval("`~
~`.subckt opamp_parax VDD ZREF vin_n vin_p Vout VGND`~
~`.include [file normalize ../mag/opamp.sim.spice]`~
~`.ends)"`~
~will solve the issue~

~may be there is some option in the extraction to add the .subckt /.ends lines? <@U016EM8L91B>~

but I see the subckt in the sim spice: <https://github.com/mattvenn/tt06-fet-opamp/blob/82dd28a2e4d76ff9cb7e8f59b8f2cc4b2fb4b003/mag/opamp.sim.spice#L3>

Ah, this makes all my assumptions wrong.. will check the file...

<@U0172QZ342D> the opamp_parax symbol instance lack a name=... attribute.
Add `name=x2` and you will be ok.
since there is no name attribute it will get the default name=x1, but there is already a name=x1 in the design (the opamp symbol).

1.png

yes, confirmed that was the issue and now it works

May be it would be nice to raise a warning in these cases, since tracking the error from ngspice error messages is not easy :smile: