I'm trying to pass what's essentially just two poly resistors through the precheck on the efabless site for an analog design. I've made a repo by cloning from https://github.com/efabless/caravel_user_project_analog. I previously had errors:

[04/05/24 12:01:36 PDT] FAILURE
                4 Check(s) Failed: ['Consistency', 'GPIO-Defines', 'Klayout Offgrid', 'LVS'] !!!

I know the GPIO_Defines can be fixed by setting the

USER_CONFIG_GPIO_<val>_INIT

pins to

GPIO_MODE_USER_STD_ANALOG

, (aside from GPIO_5 and GPIO_6 which I've set as

GPIO_MODE_USER_STD_NOPULL

) in the verilog/rtl/user_defines.v file. The consistency error:

STDOUT: LAYOUT CHECK FAILED: The GDS layout for user_analog_project_wrapper doesn't match the provided structural netlist. Mismatching modules are: ['Bridge_Only']
STDOUT: {{NETLIST CONSISTENCY CHECK FAILED}} user_analog_project_wrapper netlist failed 1 consistency check(s): ['LAYOUT'].
STDOUT: {{CONSISTENCY CHECK FAILED}} The user netlist and the top netlist are not valid.

I don't have the user_analog_project_wrapper.spice in the netgen folder setup properly. I tried to add the symbol for my Bridge_Only schematic using xschem as shown in the attached image and generated the netlist with the LVS netlist: Top level is a .subckt option checked under the Simulation tab in xschem. The netlist generated is attached. Running the precheck again results in an exception:

[04/05/24 14:29:22 PDT] SUBMITTED
                


        
    
        
            

            [04/05/24 14:34:00 PDT] STARTED
                


        
    
        
            

            [04/05/24 14:34:03 PDT] PROJECT GIT INFO
                Repository: https:/repositories.efabless.com/smay26/analog_tester2.git | Branch: main | Commit: 592474114e8671f695853eda6bd33bcef85f2d60


        
    
        
            

            [04/05/24 14:34:03 PDT] EXTRACTING FILES
                Extracting compressed files in: analog_tester2.git


        
    
        
            

            [04/05/24 14:34:03 PDT] PROJECT TYPE INFO
                analog


        
    
        
            

            [04/05/24 14:34:03 PDT] PROJECT GDS INFO
                user_analog_project_wrapper: 5d5563dde4f24dcb263103048bcb40f8a74189eb


        
    
        
            

            [04/05/24 14:34:03 PDT] TOOLS INFO
                KLayout: v0.28.12 | Magic: v8.3.465


        
    
        
            

            [04/05/24 14:34:03 PDT] PDKS INFO
                SKY130A: 49d3c73c2cd8ea42cdae5056440baef0f72e7e42 | Open PDKs: 12df12e2e74145e31c5a13de02f9a1e176b56e67


        
    
        
            

            [04/05/24 14:34:03 PDT] START
                Precheck Started, the full log 'precheck.log' will be located in '/mnt/users_data/jobs/smay26/analog_tester2/255b59c0-0691-4263-8dd8-55876a625267/logs'


        
    
        
            

            [04/05/24 14:34:03 PDT] PRECHECK SEQUENCE
                Precheck will run the following checks: [Makefile, Consistency, GPIO-Defines, XOR, Magic DRC, Klayout FEOL, Klayout BEOL, Klayout Offgrid, Klayout Metal Minimum Clear Area Density, Klayout Pin Label Purposes Overlapping Drawing, Klayout ZeroArea, OEB, LVS]


        
    
        
            

            [04/05/24 14:34:04 PDT] STEP UPDATE
                Executing Check 1 of 13: Makefile


        
    
        
            

            [04/05/24 14:34:04 PDT] MAKEFILE CHECK PASSED
                Makefile valid.


        
    
        
            

            [04/05/24 14:34:04 PDT] STEP UPDATE
                Executing Check 2 of 13: Consistency


        
    
        
            

            [04/05/24 14:34:09 PDT] EXCEPTION
                Script error code: 1

Hi @Sean May Probably a good question for #shuttle-precheck. 😉 The consistency check is checking that the top level of the gds matches the top level of the schematic. Not sure why you’re getting an exception there. You might need to change the subcircuit name so that the case matches the layout

bridge_only

->

Bridge_Only

. Do you have the same problem with the local precheck?

make precheck
make run-precheck

Apologies for posting in the wrong channel again. I adjusted the .gds to have the case match the netlist as

bridge_only

. Running the local precheck gets:

@Sean May Can you post your current

netgen/user_analog_project_wrapper.spice

file?

user_analog_project_wrapper.spice

@Sean May The latest problem is a local precheck result, right? Do you have

MPW_TAG

defined? If not, what is the

MPW_TAG

in the project

Makefile

.

Yes the latest problem is from the local precheck. The MPW_TAG is:

MPW_TAG ?= mpw-9h

Looking into it now. Can you share your gds?

Shared as a direct message.

@Sean May Sorry to take so long for the reply. I think there are a few issues with the

caravel_user_project_analog

Makefile. After making some changes to the Makefile, I was able to duplicate your results. Looking into the actual cause now.

Your help is much appreciated, the delay is no issue I am just trying to figure out how to get something to pass all the checks on something simple at first. Removing all comments from

netgen/user_analog_project_wrapper.spice

does fix the issue with the exception and my consistency checks have passed. I get an

{{SPDX COMPLIANCE CHECK FAILED}}

statement now, but have read this isn't critical to pass. I still have the`Kalyout Offgrid` and

LVS

checks failing. It's not apparent to me how to find the offgrid violations from the xml

klayout_offgrid_check.xml

. I'm not sure how to resolve the LVS issues, I don't plan to use any of the

wbs

or

la_data_i/o

pins, but do want to use

gpio_analog

pins. I've attached the offgrid.xml and lvs.report files. Thank you again for helping here.

@Sean May for the off grid check results, load the gds into klayout, and then

Tools

->

Marker Browser

and choose the

xml

file. LVS is using the default spice netlist (a power on reset circuit). Check

LVS_SPICE_NETLISTS

setting in the

lvs/user_analog_project_wrapper/lvs_config.json

file.

Thank you very much again for your help. I was able to fix the offgrid issues by setting the grid size to 0.1um in magic before generating the .gds for the resistors I'm using. For some reason every corner of each polygon in magic generated sky130_fd_pr__res_xhigh_po resistors were offgrid. I adjusted the

lvs_config.json

to have

"$UPRJ_ROOT/netgen/bridge_only.spice"

as the only entry under

LVS_SPICE_FILES

. The

xschem/user_analog_project_wrapper.spice

file was not updated which is the entry under

LVS_SPICE_FILES_TO_FIX

updating this removed some of the errors, though I'm still not passing the LVS check.

@Sean May Fortunately, the fix should be relatively simple. The

LVS_SPICE_FILES_TO_FIX

was originally implemented to change the fixed width resistor models into generic models that match the extracted models (with L and W parameters). However, last year magic was upgraded to extract the fixed width models making

LVS_SPICE_FILES_TO_FIX

obselete. Try moving

xschem/user_analog_project_wrapper.spice

to

LVS_SPICE_FILES

(don’t forget the

,

).

Thank you for the help here again, I adjusted the .json with your recommended change. Still had issues with the LVS check, but have managed to pass all the checks for this simple design. I think I had issues with the

res_xhigh_po

resistors not having the body terminals connected properly in the gds. Adding mcon to connect the ring of li1 generated by magic to one of my ports seems to have solved a LVS mismatch error.