hi folks, thanks for being helpful all this while. I was doing the simulation for a testbench in ngspice. however, ngspice shows this message. fyi, I generated the spice file after checking the "LVS netlist: top level is a netlist" option. (the spice file is given alongside)

@Himanshu Singh Does it work with

LVS netlist: top level is a netlist

unchecked? I don’t think you’ll be running LVS on the test bench, just using it for simulation.

yes it works with the option unchecked. I noticed that when I check the option, the nfet/pfet descriptions become concise. why does the tool do so?

Each of the symbols probably has 2 format options - one for lvs and one for simulation. lvs doesn’t need many of the parameters. Open a symbol and press

q

to see the formats.

@Himanshu Singh the option LVS netlist is only for Layout vs Schematic checking (LVS). For simulation leave it unchecked. There are different formats for simulation and LVS. Layout vs schematic netlist does not need many parasitic D/S capacitance estimations, just wants geometrical dimensions, number of fingers and multiplicity. For simulation netlists xschem puts in reasonable estimations for junction area and perimeter for drain and source terminals. The simulator uses these informations to better estimate parasitic capacitances and resistances.

ok , got it. thanks @Stefan Schippers , thanks @Mitch Bailey. i owe you one