@Stefan Schippers, I was looking to do mixed signal simulation in xschem. I was wondering if there is a way to import verilog(.v) file in xschem or can i create verilog file in xschem and is there any documentation for writing verilog code in xschem??

@Matt Venn got a mixed-signal simulation working in ngspice-42 and I think has a writeup on it somewhere. The co-simulation in ngspice version 42 only allows one verilog file to run alongside the SPICE. This works well for setting up a testbench in verilog to control digital signaling to an analog block. However, if you have digital blocks that are synthesized and embedded in the analog, then the best approach is to convert them to xspice and subsitute the xspice netlist for the SPICE subcircuit for those blocks only.

@Tim Edwards Yes , I have synthesized digital block. While synthesizing digital blocks in openlane, I have added dummy verilog file of analog circuit with only pins info in that verilog file. So , I need to convert the synthesized .v file to xspice for simulation..right?