Hi, I'm trying to use ngspice to run verilog designs on analog simulations but I'm not sure if there's support for systemverilog files, since the generated .so from "sigma_delta_counter.sv" has no name, it's just

.so

# Generates adc.so
$ ngspice vlnggen adc.v

# Only generates a .so
$ ngspice vlnggen <http://sigma_delta_counter.sv|sigma_delta_counter.sv>