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Hi All, I am trying to do LVS on a simple circuit but it fails pin matching and only output I get is...
# analog-design
n
Hi All, I am trying to do LVS on a simple circuit but it fails pin matching and only output I get is : 
"DEVICE mismatches: Class fragments follow (with node fanout counts):"
Can anyone please help me with the issue?
t
The difference is in which input signal connects to which pFET device in the series stack of two pFETs between power and output. Both circuits are logically correct. But netgen is matching topology, so having the same input go to the same device is important.
m
@naina singhal I suspect that the inputs to the nor gate are swapped. netgen does not do mos permutations (if you’re familiar with Calibre). In the schematic, 
INDEL
input is closest to 
VDD
, but in the layout, 
OUTDEL
is closest. (as @Tim Edwards just said).
n
Ok. Thank you so much @Tim Edwards @Mitch Bailey 🙂
Hey @Tim Edwards and @Mitch Bailey sorry to disturb you again. But I have one more LVS issue. In my final design, there are some property errors : one of them is present is because 
instance sky130_fd_pr__pnp_05v5_W3p40L3p40:Q1 property "m" has no match in circuit 2
 and other is because of the property errors in dummy transistors. Can you please have a look at them. Even though the circuits match, will these errors cause the precheck to fail?
t
@naina singhal: Interesting. The PNP property error only shows up if you put the schematic first and the layout second when running LVS. If you put the layout first and the schematic second (which is the usual way), then that specific error disappears. It looks like a bug in netgen, although one that is easy to work around (while I go looking for a proper fix to the code).
I found and corrected the error in netgen (in new version 1.5.273). The issue was (as I expected) a failure to make the code symmetric between comparing processes for the 1st and 2nd netlist, and adding the code to make it symmetric solved the issue.
👍 1
Thank you for reporting the bug.
👍 1
n
Thank you so much for the fix @Tim Edwards
@Tim Edwards What about the property errors in dummy transistors. I have looked but I can not find any issue. Is it because of the old version of netgen? I am using 1.5.262.
t
Good question. I was concentrating on the other error, so I didn't look at that one. From the output, it looks like netgen retained the AD, AS, PD, PS parameters from one of the netlists, which it was supposed to ignore. The presence of those parameters is probably what's preventing netgen from merging the devices by adding the widths together.
n
oh ok...
t
I will need to investigate, and will see if I can debug it later today.
n
Ok. Thank you.
t
Okay, I tracked this one down, too, and it was a bug in the device sorting algorithm. I have fixed that one, too. Both changes have been pushed to the netgen repository at opencircuitdesign.com. The github repository will be updated by a mirror copy in about 6 hours.
🎉 2
n
Ok. That is awesome. Thank you so much.🙂
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