I don't know what you did, but if you did what I said, it would have worked. I added this to the top of `core_layout.spice`:

* Black-box entry for ReRAM cell
.subckt sky130_fd_pr__reram_reram_cell TE BE Tfilament_0=3.3e-9 area_ox=0.1024e-12
.ends

although for a long-term solution, it works best to keep that in a separate cell and write an LVS script that reads it into netgen during LVS.