Because the ReRAM device at the level of

sky130_fd_pr__reram_reram_cell

in the layout has pins "TE" and "BE", you need to read the device definition into the schematic netlist from

$PDK_ROOT/sky130B/libs.ref/sky130_fd_pr_reram/spice/sky130_fd_pr_reram__reram_cell.spice

. But the SPICE netlist has a zero-valued resistor component in it which is likely to cause netgen to treat it as a short across TE to BE. Netgen probably won't read the verilog netlist correctly, either. You probably will need to make a black-box entry locally for the ReRAM device and read that into the schematic netlist. Basically, just this:

.subckt sky130_fd_pr_reram__reram_cell BE TE
.ends