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Here are two test cases of the same base layout, t...
# chipalooza
r
Here are two test cases of the same base layout, the only difference is how Dnwell is setup. https://github.com/ajcci/sky130_ajc_ip__overvoltage/tree/main/mag The first one 
comparator_shared_dnw.mag
has a single DNW region covering everything. This does not produce the expected result. Two separate pwell regions on different nets got shorted, one named 
avss
and the other named 
vt
. In the extracted netlist 
comparator_shared_dnw.spice
the node 
vt
is missing, and what is supposed to be 
vt
became 
avss
. In the second example, 
comparator_separate_dnw.mag
has separate DNW regions for nfets tied to different pwells. One for nfets in a pwell connected to 
vt
, and one for nfets in a pwell connected to 
avss
. In the extracted netlist 
comparator_separate_dnw.spice
, both 
vt
and 
avss
are connected accordingly as expected. Regarding hierarchy, for all the nfets, I used the pcell generator to create them and each nfet is in their own cell in the layout. As for flattening, yes it helps and works if I flatten. Thanks for the help and suggestions!: @Tim Edwards @Luis Henrique Rodovalho
t
Okay, the underlying problem here is that there is no actual PWELL layer in sky130. The drawn "pwell" in magic is effectively an identifier that helps magic determine where devices share a pwell or substrate (although most of the related issues got fixed a while back). If you removed the pwell layer in magic, you would still have the same circuit. The upshot is that anything inside "dnwell" that is not inside "nwell" is a P-region. Your two regions in the shared DNW really are shorted together. If you want them to be separate, then you need to separate them with an nwell. Each P region should be completely surrounded by an nwell ring, and then they will be electrically separate. (Your interpretation of the deep nwell is correct for GF180MCU; it really depends on how the foundry defines the deep nwell layer.)
Although that raises the question of what it means that you say it "works if I flatten". According to what I just said, if you flatten the 
comparator_shared_dnw
layout, it should still merge the pwell regions together.
r
Thank you Tim, now I understand better. Sky130 requires a complete nwell-surround in order to isolate psub connections from one another, whereas gf180mcu does not. I will give it a go and draw nwell in between the two p-regions and make sure each is completely surrounded. As for flattening, I will try to put up a test case to demonstrate what I saw. It was tested with single transistors on a separate layout when I was trying to figure out what was going on. I remember the pwell connection in the extracted netlist behaved differently based on whether or not the layout was flattened. And the flattened version produced a netlist I was expecting.
@Tim Edwards Hi Tim, thank you for your time and patience once again. I am happy to report that it was user(my)-error in both tests that I did. (1) For the test case where all circuits share the same Dnwell, all I have to do is draw a ring around the nfet where the nfet's psub connection is not connected to ground (using the Dnwell pcell generator). Its basically a ring inside another ring, with the outer ring being the Dnwell-surround of the entire circuit. It works great now. (2) For the test case where it worked when flattened, tracing back my steps, I think what happened was I failed to put a piece of locali paint over the pwell-tap before dropping the label at the top cell. Since the pwell-tap is within the nfet's cell, the label never made the connection. But when the entire layout was flattened, the label attached correctly. It was user-error.
t
Sanity is restored. Thanks for reporting back! I have yet to understand for the GF180MCU process what, exactly, is inside a deep nwell when neither NWELL or LVPWELL is drawn. Maybe it's just that I haven't read the GF documentation as many times as I have the SkyWater documentation. . .
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