hey so i am new here again so sorry if i dont know the right way to ask for help but i am trying to synthesize a 4-bit counter from JK flip flop modules and these are the Verilog files counter_4bit.v

module counter_4bit (
    input clk,
    input rst,
    output reg [3:0] count
);

reg [3:0] q0, q1, q2, q3;

JK_flipflop ff0 (.J(q0), .K(1'b0), .clk(clk), .rst(rst), .Q(q0));
JK_flipflop ff1 (.J(q1), .K(q0), .clk(clk), .rst(rst), .Q(q1));
JK_flipflop ff2 (.J(q2), .K(q1), .clk(clk), .rst(rst), .Q(q2));
JK_flipflop ff3 (.J(q3), .K(q2), .clk(clk), .rst(rst), .Q(q3));

always @(posedge clk or posedge rst)
begin
    if (rst)
        count <= 4'b0000;
    else
        count <= {q3, q2, q1, q0};
end

endmodule

JK_flipflop.v

module JK_flipflop (
    input J,
    input K,
    input clk,
    input rst,
    output reg Q
);

always @(posedge clk or posedge rst)
begin
    if (rst)
        Q <= 4'b0000;
    else if (J & ~K)
        Q <= 1'b1;
    else if (~J & K)
        Q <= 1'b0;
    else if (J & K)
        Q <= ~Q;
end

endmodule

config.json

{
  "DESIGN_NAME": "counter_4bit",
  "VERILOG_FILES": [
    "dir::counter_4bit.v",
    "dir::JK_flipflop.v"
  ],
  "CLOCK_PERIOD": 25,
  "CLOCK_PORT": "clk"
}

i ran the command

openlane ~/my_designs/jkcounter/config.json

and i get an error that GPL exceeds 100% could some one tell me what i did wrong/how to fix it?

To synthesize something there needs to be a sythnesis target for it. I'd suspect that if you look in the target PDK std cells list you might find there is no JK flip flop. 99% of all sync design is done using DFF and about 90% of what is done with anything other than DFF is done with an RS latch. Check your target library and see if it has what you need.