I got back my test Caravel Openframe project from the chipIgnite 2309 run. The project is this one: https://github.com/RTimothyEdwards/caravel_openframe_project (although I think the fork at https://github.com/efabless/caravel_openframe_project reflects the state of the project as it went to tapeout). It implements a PicoRV32 with 4kB (2 x 2kB) OpenRAM macros. It was designed to be compatible with the Caravel architecture and basically mimics the (intended) function of the original MPW-1 chip. I plugged it in and was immediately able to talk to the housekeeping SPI. It took me only a few minutes to work up a "blink test" program and flash it. Everything went flawlessly. I have now confirmed operation of the GPIO, the UART, the DLL, and the SRAM (all at nominal conditions; no stress tests yet). I still need to test the QSPI operation and a few other features.

all IOs checked?

Not yet. I have been working on this during meetings and in spare time because I have too many other things to do. But I'll see if I can get a full accounting of all the I/O. However, every I/O other than the ones with dedicated functions (like the SPI flash controller) are done the same way, so if I can run the blink test, then I shouldn't have any issues with the other I/Os, either. But of course that needs confirmation.