What are the hard / time-consuming parts of layout...
# chipalooza
l
What are the hard / time-consuming parts of layout? I know almost zero about it and so far I just see straightforward rectangle-drawing haha
p
The most challenging part from an optimization point of view is good floorplanning in layout (its more of an art than science in analog) Post floorplanning (placement of different components over the design/die area), routing (connecting the components using metals/interconnects such that the connections are as in the schematic) is the tedious part of layout. This tedium tends to grow with the number of signals.
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Most issues arise post layout completion in the parasitic extracted simulations where extra capacitances, resistances (and inductances for rf circuits) cause deviations in the circuit behavior
l
Is there any good short intro material that would give me very very rough intuitions about how to anticipate layout problems such as parasitic capacitance?
I'm thinking my usual approach of randomly trying stuff over and over until something works may fail for layout.
p
I have learnt layout from my day job and don't have too many publicly available resources to suggest except for "Art of Analog Layout - Alan Hastings". You can find a copy of this on the interwebs ๐Ÿ˜…
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