Hi, I am trying to run LVS on an inverter that I created in xschem and the layout in magic. I've read a few other similar posts about the same issues that I'm having, but I cannot seem to get it to work. I'm capable of running LVS between the two spice files, but it always tells me that there are no pins in my cells. I've seen that I need to include the pins on the . subckt line in the spice files, but when I include that line in my spice files, then the lvs states that my spice file contains no instances, devices, or nets. Any help would be greatly appreciated.

It would be much easier to help if you put it in a repo and post the link so it can ne easily reproduced

@rdiciro Can you share the command that you use to run LVS?

lvs

is a shell command that calls netgen, right?

Hi @Mitch Bailey I've been working on this still for a bit but havent made much progress. I checked off the

Simulation -> LVS -> LVS netlist: top level is a subckt

option in xschem and got the spice file again. When I run LVS now I get output that my two files have devices and nets but now it says that there are no pins and that pin matching isn't needed even though I have them.

@Roderick DiCiro The

inv_schem.spice

netlist does not look like it was created with the

LVS netlist

option. Check the timestamp to be sure it’s the right file.

inv_layout.spice

is not extracting ports. Does your layout have ports? Also, please share your lvs command.

@Mitch Bailey I mispoke sorry I unchecked the

LVS netlist

option. I belive my layout does have ports. I start netgen and my lvs command is

lvs inv_layout.spice inv_schem.spice sky130A_setup.tcl

@Roderick DiCiro When the subckt names that you want to compare are different use

lvs "inv_layout.spice layout_test" "inv_schem.spice inv_no_sim" sky130A_setup.tcl

The top layout appears to be

layout_test1

. Is that a flattened layout? Text in magic is not necessarily a port. You need to use the

make port

command, I think.

@Mitch Bailey sorry I have them named something different in my VM I changed the names to help tell which was which. I use the lvs command

Is the top subckt name the same in both your spice files?

No, so I should still use the same command as you said earlier, right? The layout file does not have a subckt line in it.

Are the yellow markers at the top, left, right, and bottom the ports?

I believe so *Edit:: No they are not I think they might just be labels I will make them ports now

@Roderick DiCiro I don’t think you want to flatten the layout.

extract
ext2spice lvs
ex2spice -o layout_test1.spice

@Mitch Bailey Looks good now! Now for running lvs again, I should remove the the ** on the subckt line and the .ends line in the inv_no_sim_not_top.spice file and then run

lvs layout_test1.spice "inv_no_sim_not_top.spice inv_no_sim" sky130A_setup.tcl

, right?

The ports on

layout_test1

are still not being extracted. Shouldn’t need to manually edit

inv_no_sim_not_top.spice

if you set the

Simulation

->

LVS netlist: top level is a .subckt

before netlisting.

@Mitch Bailey Do the ports on the layout need to have a direction set as well? I was looking through the port command options on magic. Also when I select the

LVS netlist:

option and run LVS with that file changed it says that it has no elements or nodes

Not sure if a direction is needed or not. They should show up as ports in the final netlist.

@Mitch Bailey I think I figured out the issue. When I was making the layout for the inverter I had saved the pins and connecting layer to the cmos cell instead of the top level cell. I have fixed the issue and I believe I have gotten the pins to extract correctly.