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Hello everyone, I was trying to run lvs for a test dflipflop made of standard cells using a script i...
# lvs
c
Hello everyone, I was trying to run lvs for a test dflipflop made of standard cells using a script i found on the slack. When I try to run the lvs script with 
netgen -batch source setupfile.tcl
, I get the attached error. Does someone know what I might be doing wrong with how I am running the lvs? If I look at the comp.out by using 
netgen -batch lvs "magic/dflipflop.spice dflipflop" "schem/dflipflop.spice dflipflop" /path/sky130A_setup.tcl
I notice that the standard cell spice file does not use the standard port names for both schematic and layout. Could this be the problem or might it be something else?
setupfile.tclcomp.out
schem_dflipflop.spicemagic_dflipflop.spice
m
@Charles Devoite The 
setupfile.tcl
looks basically good. The only thing that concerns me is the backslash in the netgen command. Can you try without it?
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lvs "$circuit1 dflipflop" "$circuit2 dflipflop" $setupfile lvs/comp.out
The one line netgen command with batch is trying to compare a fully extracted layout with a schematic that has the standard cells abstracted - there’s no way for netgen to get the subcircuit port names. A temporary (but not recommended) solution would be to 
.include
the spice library in the netlist created from the schematic. The preferred method is to use the script and load the files separately.
c
@Mitch Bailey I have gotten the script working, it seems that I used a capital somewhere that I did not notice. However, the layout that is created does not contain any taps, since this would result in lvs mismatch. I made a small testbench to figure out, what is going wrong. In this setup I am using a small script to create global variables for my VPWR etc. This results in the attached graph for a simple 3 input "and test cell", without using taps and extracting with a cthresh of 0. (the right side is a normal simulation) Do you know how I could add the taps into my design? I tried to use the stdcell "tapvpwrgnd_1" for the layout, but is there a corresponding symbol for xschem?
m
@Charles Devoite if you’re doing LEF based extraction, the 
tapvpwrgnd_1
cells will be extracted. I can’t remember seeing a symbol for use in xschem analog designs. Shouldn’t be too hard to create though. By default, extracting from gds or mag files does not create a 
tapvpwrvgnd_1
cell. You can force extraction by setting the 
LEFview
property. Another method is to use a verilog module for your standard cell circuits, create a symbol for that and include the verilog file in your lvs script.
c
@Mitch Bailey I am using the standard ext2spice extraction method for creating the netlist. Extraction without the 
tapvpwrgnd_1
cells seems to work fine and I can simulate that with some expected errors. When I try to incorporate the 
tapvpwrgnd_1n
cell, I get lvs mismatch since the xschem standard cells have no connection between those four. Since I want to use some standard cells in my analog design I would like to be able to have the 
tapvpwrgnd_1
inserted in the subdesigns so that no mismatch occurs. How could I do this? Would you say that a verilog module is the only way to do this or is simply possible to add a small script inside the xschem symbol that includes VPWR=VPB for example?
m
Let me respond in the morning.
From what I’ve seen, using standard cells in analog (xschem) schematics requires adding a property to the symbol like this
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VGND=vss VNB=vss VPB=vdd3v3 VPWR=vdd3v3
If you have no tap cells in the layout, these 4 nets will all be different. If you include tap cells, you can set the values for ground and the values for power to be the same as above. The layout tap cells do not contain any devices, but do short the substrate/well connections to ground/power respectively. It might be kind of tricky to come up with some system of shorting nets in the schematic through tap cells (maybe a 0 ohm resistor would work). Because of this, all the designs I’ve seen have common ground/substrate and power/well connections in the schematic and include a tap cell in the layout. In order to pass full chip LVS (which abstracts the tap cell and checks the tap cell counts), you can either include a 
tapvpwrvgnd_1
primitive symbol in the schematic (with m=<number of instances>), or you could place the tap cells and then flatten them, or change the cell name (only the default tap cells used in digital design are abstracted). So my recommendation is to copy the digital tap cell to an differently named analog tap cell, place those in the layout, and modify the properties on your digital symbols to connect VGND/VPW to vss and VPWR/VNW to vdd.
c
Thank you very much for your response, I found a working solution in changing the names locally instead of globally.
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