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<@U01819B63HP> I am trying to vary a parameter `vc...
# xschem
v
@Stefan Schippers I am trying to vary a parameter 
vctrl
in testbench using 
alterparam
and plot output waveforms. This testbench was working fine earlier but now could not see waveform with value defined with alterparam or some issue in plotting waveform. Can you please suggest what could be issue here ?
inv_delay01.sch
s
@vks the fixed schematic. You can do a diff of the two files. 
save
and 
save all
lines are better placed out of the .
control / .endc
, otherwise you have to repeat these lines after a reset instruction. Don't ask me the reason for this 😄
inv_delay01_fix.sch
👍 1
v
Ok, thanks very much. I have used hspice in past, ngspice definitely is not that straight forward. I am facing issue of recurring crash of xschem while working on this design. Have updated xschem to latest version but still it is persisting. Any suggestions on this ?
@Stefan Schippers Your shared schematic file is running fine. I implemented same suggestions in this schematic by keeping 
.save
out of 
.control
block. But same issue is coming again in this schematic. Why this issue is coming now?
inv_delay.sch
s
@vks can you please tell what actions are causing the crash?
v
@Stefan Schippers I tried implementing same steps as followed in your video but issues still persists. This looks very strange. The crash was also happening while trying to netlist same schematic 
inv_delay.sch
.
Recording 2024-03-21 160357.mp4
Please see latest updated schematic and netlist files generated from above shown simulation.
inv_delay.spiceinv_delay.sch
s
@vks what is the ngspice output?
v
Here is ngspice output
s
You see the reason: Error: measure tdelay01 trig(TRIG) : out of interval the second run circuit does not oscillate enough
👍 1
add 
uic
after the tran lines and it will be ok: 
tran 0.001n 100n uic
👍 1
v
Thanks very much @Stefan Schippers for debugging the issue. Just for curiosity why this issue didn't came in simulation run in your video which was run without use of 
uic
. Is there any shortcut command for 
xschem ->Simulation->Graphs-> Annotate operating point in schematic
?
s
ring oscillators have a meta stable condition where all inverters are stuck at Vin = Vout = ~= Vcc/2 a small peturbation like thermal noise will move the ringosc out of metastability, but a simulator is ideal does not generate noise (if not told to do) so in some cases the circuit may get stuck. In some cases adding a .ic v(out4)=... may resolve the issue. For better behavior add dummy loads on all inverters so they will generate identical outputs The startup of a ring oscillator is quite unpredictable, in some cases the circuit will not oscillate at all, being all outputs stuck at the inverter threshold. In real world this won't happen due to noise that will quickly bring the system out of metastability. In real devices oscillators always have an enable signal to start oscillation. You can for example replace all inverters with NANDs and use an 
enable
signal on one NAND input while keeping all other nand secondary inputs to VCC.
inv_delay.sch
v
@Stefan Schippers I again encountered xschem crash. Attaching log files as highlighted in crash message in below screenshot.
xschem_emergencysave_inv_delay_gbdbdecfcg.tar.xz
s
the provided inv_delay.sch has a 'Annotate OP' launcher to do OP annotation
👍 1
I again encountered xschem crash. Attaching log files as highlighted in crash message in below screenshot.
Thank you, @vks. if you have the xschem sources can you do a 
git show HEAD
in that directory and tell me what commit you are using?
Copy code
schippes@asus:~/xschem-git$ git show HEAD
commit 85abc67c898251fd321c07fd11255447ff860141 (HEAD -> master, origin/master, origin/HEAD)
Author: stefan schippers <stefan.schippers@gmail.com>
Date:   Thu Mar 21 01:28:01 2024 +0100

    fix arc placement if moving mouse to the left for second point
v
I am getting this output running 
git show head
command.
Hope this helps
s
Thank you. I need to try the sequence of commands that triggers the problem. If I get xschem to crash problem is usually close to be solved :-)
@vks I was able to crash xschem on your example. It happens to me after changing some commands in the code block and extracting the netlist. Is the same for you!
@vks, Please update xschem, I found the reason for the crash and it is now fixed. Thank you for support.
👍 1
v
Thanks @Stefan Schippers, I will update xschem tomorrow and work on same design which was causing crash today. Will update you on this issue tomorrow.
s
Thank you!, you discovered a serious bug, and I think it is now gone (ready for the next one).
v
Sure, will continue to provide updates as delve deeper into xschem-ngspice. I found it quite gratifying how swiftly the bug was identified, reported, and fixed. With expensive commercial tools, bug confirmation and resolution could have taken months in a new release. Had some frustrating experiences with them in past. @Stefan Schippers @Tim Edwards @Matt Venn
s
In the mean time while doing stress tests to find the crash I have created a 5 stages ringosc made with identical NANDs and an enable signal, + equal dummy loads on all stages to have symmetrical behavior. Your original inv_delay was extremely big , may be there is a specific reason for that ( very high frequency operation?). I used smaller transistors to reduce Icc consumption a bit (300uA at 440MHz). Anyway I just wanted to show the enable function. Asserting enab will make the oscillator start immediately, you don't have to wait for some numerical noise to kick in and start the circuit.
inv_delay5.sch
👍 1
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