Hi all. I have one question in layout design. In power nets is there any rule for via spacing in via array or grid (other than DRC) to reduce high current density. For example please look at the image attached. What is better way for dropping vias in power nets 1 or 2. Or is there not much difference?

Some processes require larger spacing for arrays larger than a certain size, but Sky130 doesn't. They do not have wider spacing in the I/O cells where there is clearly a high current density.

Ok. So there is not much difference. I saw couple of layouts in caravan wrapper where there was larger space between vias in grid. I was curious. What about in case of via array stacking? Thank you so much for your answer.

@naina singhal one merit of magic is that you don’t need to draw(paint) individual vias. You can draw a large via area and when you stream out, via areas are filled with correctly sized and spaced vias.

It's magic!

Ok. Thank you so much @Mitch Bailey