@Tim Edwards I have some questions about the specifications of the 1.8V Bandgap too. Since I am using a CMOS voltage reference, the vref will probably not be exactly 1.2 as in a real bandgap circuit, so: 1. I think I will need to scale the voltage using some sort of CMOS voltage divider or even a full amplifier with feedback, which may get complicated, will these specs be considered critical? 2. Not sure yet if my circuit produces an Iptat, because a vptat is produced using a self-cascode mosfet. I will look into the bias current that I have in the mirrors, but I think they will be proportinal to specific current (sorry for the lack of info, I am working on too many thinks at once) 3. For the scaled voltages, am I expected to just resistor-divide Vbg? Sorry for the beginner question, but if anyone can sugest a better voltage scaling technique, preferably cmos-only, I think I still have time to look into it. 4. What about Rload/Cload, am I missing something or they were not specified? Wouldn't Load regulation need to have some specification of output current or resistance ranges?

Your CMOS reference is a bit "out of the box" compared to the specification. It is an interesting alternative to the bipolar bandgap, so I decided to accept the proposal and let you go ahead with the design. The output voltages would need to be the ones specified if we were going to use that bandgap for distributing biases across the chip, since the other blocks are going to expect the output voltages (and currents) specified for the bandgap block. If you can generate those voltages, that would be helpful, but I wouldn't consider it a priority. Somehow the load condition got lost from the load regulation spec. Sorry about that. For you and @Alexandre Menu, let's assume a load current minimum of 100nA and maximum of 1uA.