I have this as a top level LVS: https://github.com/mattvenn/tt06-analog-r2r-dac/blob/main/mag/tcl/lvs_netgen.tcl

which is run by a rule in the Makefile in ./mag

now that works to do LVS on the wiring, but if I break the r2r block internally, it's not detected

If I comment the 'readnet verilog' and uncomment the 'readnet spice' and set project to 'r2r' then LVS will run against just the r2r block and can detect the broken r2r block

so my question is how can I do a complete LVS that includes the cells in the hierarchy?

Ideally I want one make rule and one tcl file that does it all

I'm not getting a comp.out file in the process

I've also realised that the openlane block is not getting checked either, because I just deleted the gate level verilog and the test pass. So I think the only thing that lvs is doing at the moment is the top level wiring

(Aside: Why is the structural verilog in the

mag/

directory?)

Actually, that's not so much of an "aside". . . If you keep the "standard" filesystem formatting and have directories

verilog/rtl

and

verilog/gl

("gl" = "gate level"), and all of your synthesized blocks end up in

verilog/gl

, then you can have a generic script that simply reads every file from

verilog/gl

into netgen.

and added the extra spice and GL verilog to the lvs script: https://github.com/mattvenn/tt06-analog-r2r-dac/blob/main/mag/tcl/lvs_netgen.tcl

how would I adapt the tcl file to read all the spice in ../xschem/simulation and all the gl verilog in ../verilog/gl ?

well actually I don't want all the spice in ../xschem/simulation because that includes the testbench

I'm trying to make the script generic but maybe this isn't useful