<@U020J2W6Q84> Is there a way to disable some warn...
# openlane-2
t
@donn Is there a way to disable some warnings ? I get a lot about modules being blackboxed (no netlist/ no libs) but that's on purpose, I want them blackboxed, so having the final output filled with hundreds or irrelevant warnings is a bit annoying because it hides real infos ... Also get :
Copy code
[08:54:59] WARNING  'PNR_SDC_FILE' is not defined. Using generic fallback SDC for OpenROAD PnR steps.       flow.py:629
                    'PL_TARGET_DENSITY_PCT' not explicitly set, using dynamically calculated target                    
                    density: 27.147100…
which are also irrelevant ( no logic synthesized so density is irrelevant and I have a signoff sdc but I don't run any pnr sta or is it even relevant since again this is just wiring up macros ).
m
Have you tried
/// sta-blackbox
?
d
It won't do much in this case as he doesn't have netlists listed
t
So I get warnings for two things : • The power gates (which have just an empty module, purly to show connectivity from logic to the control signal). For those maybe
sta-blackbox
would help. • The user modules. For which I provide a fake netlist through
EXTRA_VERILOG
. That netlist is for STA purpose only and is required to create controlled endpoints I can reference in the SDC. But there is no
.lib
and not parasistics associated. And it also doesn't reflect the real module netlist, it's just a bunch of input/output buffers connected to nothing.
Adding
/// sta-blackbox
did nothing, looking at the code this is ignored for macro where the netlist is given in the
nl
key of the dict and only checked for
EXTRA_VERILOG_FILES
Moving the power gate verilog to
EXTRA_VERILOG_FILES
did reduce some of the warnings, but the one from
No libs found for macro tt_pg_vdd_1 at corner max_ff_n40C_1v95
are still present.
d
Urgh… All I can do at the moment is apologize: we are looking into the warnings situation as multiple people have complained about both OpenLanes being too shouty.