Hi people. I'm doing LVS with netgen on a metal resistor and it's giving me this warning.

Subcircuit pins:
Circuit 1: resistor_metal                  |Circuit 2: resistor_metal_clean            
-------------------------------------------|-------------------------------------------
b                                          |b                                          
r0                                         |(no matching pin)                          
r1                                         |r1                                         
(no matching pin)                          |r0                                         
r0                                         |(no matching pin)                          
---------------------------------------------------------------------------------------
Cell pin lists for resistor_metal and resistor_metal_clean altered to match.
Device classes resistor_metal and resistor_metal_clean are equivalent.

Final result: Top level cell failed pin matching.

I've already performed lvs on a poly resistor and the two mimcaps, none of them gives something like this.

@aquiles viza This is actually a poly resistor. The layout only has text at the top level and no text or pin shapes at the lower level. If you’re extracting from gds, you can specify

flatglob *res_poly

before

gds read

. The extracted layout shows that the subcircuit

res_poly$1

is only extracted with 2 terminals and that the node names are auto generated.

* NGSPICE file created from resistor_metal_clean.ext - technology: sky130A

.subckt res_poly$1 a_n703_n1362# a_n573_796#
X0 a_n573_796# a_n573_n1232# a_n703_n1362# sky130_fd_pr__res_high_po_5p73 l=8.12
.ends

.subckt resistor_metal_clean r0 r1 b
Xres_poly$1_0 b r1 res_poly$1
.ends

If you’d rather not use flatglob, you might try adding

met1

squares under

r0

and

r1

and a

li

square under

b

at the top level. My preference is to flatglob all levels that do not contain text, though.

Adding boxes of met1 and li1 solved the port problem and now it indicates

Circuits match uniquely

and

Property errors were found.

The schematic and layout has L=8 but the extracted netlist has L=8.12. This could be related with the use of guard ring? Magic command:

drc off
gds drccheck off
gds rescale false

gds flatten yes
gds read /workspaces/Chipalooza2024_TempSensor_AC3E/modules/resistor_poly_hi/layout/resistor_poly_hi.gds
load resistor_poly_hi
box 0 0 0 0

readspice /workspaces/Chipalooza2024_TempSensor_AC3E/modules/resistor_poly_hi/output/extraction/schematic/resistor_poly_hi_noprefix.spice

puts "layout loaded :)"

cellname rename resistor_poly_hi resistor_poly_hi_clean

extract
ext2spice lvs
ext2spice -o "/workspaces/Chipalooza2024_TempSensor_AC3E/modules/resistor_poly_hi/output/extraction/layout_clean/resistor_poly_hi_clean.spice"

puts "Created netlist file /workspaces/Chipalooza2024_TempSensor_AC3E/modules/resistor_poly_hi/output/extraction/layout_clean/resistor_poly_hi_clean.spice"
quit -noprompt

Extracted spice:

* NGSPICE file created from resistor_poly_hi_clean.ext - technology: sky130A

.subckt res_poly$1 a_n703_n1362# a_n573_796# a_n573_n1232#
X0 a_n573_796# a_n573_n1232# a_n703_n1362# sky130_fd_pr__res_high_po_5p73 l=8.12
.ends

.subckt resistor_poly_hi_clean r0 r1 b
Xres_poly$1_0 b r1 r0 res_poly$1
.ends

The flatglob commands didn't affect the output

The actual layout length is 8.12. Why 0.12um is added when you use the device generator, I don’t know. The flatglob command needs the name of the cell as magic interprets it. From your extracted netlist above, maybe

flatglob res_poly*

would work.

@Mitch Bailey: Within magic, declaring the label as "sticky" (

setlabel sticky

) will prevent magic from reassigning the layer type. For GDS read, the input style needs to have

options no-reconnect-labels

. I am not sure why the tech file for magic for sky130 doesn't have this option set.

setlabel sticky

and

options no-reconnect-labels

are instructions that should be set on the magicrc for all designs?

@aquiles viza: No.

setlabel sticky

should be applied to individual labels when they're created in magic (it's also a checkbox in the text GUI window under

Edit-->Text...

).

options no-reconnect-labels

has to be applied to the magic tech file; it's a setting in the

cifinput

section, and it doesn't have a command equivalent (there are a number of things in the tech file that ought to have command-line equivalents, but don't).