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Couple of questions about simulating the netlist I...
# xschem
m
Couple of questions about simulating the netlist I get from parasitic extraction. I checked this recent video:

https://www.youtube.com/watch?v=zs6JPXk074c▾

I had to rename the symbol's schematic parameter, and also the extracted netlist's subckt name. They were both 'r2r' as that's the name of the cell.
Without the rename, the 2nd symbols's output is always the same as the 1st symbol
image.png
image.png
What am I missing?
the second thing is that the waveform I get from the pex is wrong
It looks to me that the inputs to the R2R dac are out of order
image.png
I don't know why the symbols are created with the inputs all out of order. I created them in order when I drew it
If I re-order the inputs in the spice, then I get a good result
image.png
So I guess I can solve this if I can work out how to get a symbol created with the inputs in the correct order.
s
@Matt Venn I see you are setting this on the PEX symbol: 
spice_sym_def=".include ../../mag/r2r.sim.spice"
but the 
../../mag
directory is wrong (should be ../mag) and the file 
r2r.sim.spice
does not exists
Can you please check - in the 
r2r.sim.spice
spice netlist created by magic so I don't need to run the layout flow?
if the pex spice netlist is correctly recognized by xschem it will ensure that in the netlist for simulation generated by xschem the pin order of the symbol will match the pin order of the netlist whatever the order you have drawn the pins in the symbol. Only the number and names of pins must -of course- match between xschem .sym and pex netlist.
m
@Matt Venn not sure if it’s necessary with @Stefan Schippers fixes, but you can 
readspice
in magic before extraction to get the layout ports in the same order. See https://open-source-silicon.slack.com/archives/C016HUV935L/p1677358505708119?thread_ts=1677353770.126889&cid=C016HUV935L
s
@Mitch Bailey Xschem now looks into the 
.subckt
port list of the pex netlist (following the 
.include
statement or directly looking for a matching .subckt line in the spice_sym_def attribute) ) to ensure the port order is the same in the instance call (the 
X1 net1 net2 net3 ... symbol_ref
line in the xschem netlist) and the subckt line ( 
.subckt symbol_ref port1 port2 port3 ...
) from the PEX netlist. This works if the symbol has a format attribute that uses the 
@pinlist
for the list of nets (
format="@name @pinlist @symname"
) If you specify the list pin by pin (
format="@name @@CLK @@D @@RST @@Q @symname"
) then it's up to you to ensure port order correctness.
👍 1
m
@Stefan Schippers I don't think the ../../mag is wrong, because the simulation happens in ./xschem/simulation so it needs the ../../mag/
I've added the spice and pushed the repo
I know xschem is not using the pex spice file because if I change the order of the subckt ports, it makes no difference in the waves
Also, I would love to know how to get the symbol drawn with the ports in the correct order
the r2r.sch has the ports listed in order, but when I create the symbol the ports are in an odd order
image.png,image.png
m
@Matt Venn does this help? https://open-source-silicon.slack.com/archives/C016HUV935L/p1677362575347169?thread_ts=1677353770.126889&cid=C016HUV935L (You can also put the pins in order with vim in the symbol file, but I don’t think that allows the PEX netlist to work automatically.)
m
I've tried #1, which doesn't work. I can try the others
I tried adding sim_pinnumber to all the pins in the schematic and creating a new symbol, also doesn't work
maybe I mis-understood, that might only work in the symbol.
I manually moved every pin in the symbol, added the sim_pinnumber and now the spice netlist is correctly ordered. I still feel I'm missing something, shouldn't the symbol take the pin numbering from the order in the schematic?
s
@Matt Venn I have pushed a pull request that should make your example work as expected.
these are the only changes needed in the attributes of the lower r2r symbol: 
-schematic=r2r.sim
-spice_sym_def=".include ../../mag/r2r.sim.spice"
+schematic=r2r_pex
+spice_sym_def="tcleval(.include [file normalize ../mag/r2r.sim.spice])"
I have then edited 
r2r.sim.spice
changing the .subckt name from 
r2r
to 
r2r_pex
. The 
file normalize
command creates the absolute path for the file, this is needed since xschem runs in ./xschem and ngspice runs in ./xschem/simulation
m
thanks Stefan!
I rewatched that video and realised that each schematic name needs to be different
so I changed my extraction tcl to name the subckt r2r_parax and matched that in the schematic
I don't need the 
normalize
- it seems to work for me without that
the last thing I had to do was to change again the pin order of the r2r symbol, so that VSUBS and VGND were the last 2. Because otherwise when magic extracts, I get no VSUBS and so the output of the circuit is connected to ground
s
@Matt Venn the 
.include [file normalize ../mag/r2r.sim.spice]
is needed so that xschem does see the file and also ngspice does see the file. If you specify 
.include ../../r2r.sim.spice
xschem will not find the file and can not adjust the pin order of the xschem instance (the bottom r2r symbol) with the order in the 
r2r.sim.spice
file. recent xschem versions show a warning if the file can not be looked up during netlist creation. This is just a warning saying "I can not inspect the .include file to make port order match". The netlist will be generated anyway, but it's your task to ensure the port order in the symbol matches with the port order in 
r2r.sim.spice
. If you have a rather old xschem this function was not implemented.
Copy code
commit d2c6566030f8936bd7fee76d76880be7d67163de
Author: stefan schippers <stefan.schippers@gmail.com>
Date:   Mon Jan 8 03:24:59 2024 +0100

    when doing spice netlist, if a symbol has the spice_sym_def attribute set and is using @pinlist in format string for port order, get the port order from the subckt given in spice_sym_def, either directly or through a .include line
m
thanks!
will try
I just tried your suggestion and it doesn't work Stefan
If I manually edit the file to get the 'correct' order it works
I'm on XSCHEM V3.4.4
works on v3.4.5
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