Hey, I'm running through the caravel macro tutoria...
# openlane-2
c
Hey, I'm running through the caravel macro tutorial in the ol2 docs. I'm about half way through and running into this error while attempting to harden the user project wrapper
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* Antenna
Failed 𐄂
Pin violations: 45
Net violations: 45
Check the report directory of OpenROAD.CheckAntennas.

* LVS
Passed βœ…

* DRC
Passed βœ…

[22:11:02] ERROR    The following deferred step errors have been encountered:                                            sequential.py:282
[22:11:02] ERROR    hold violations found in the following corners:                                                      sequential.py:284
                    max_tt_025C_1v80                                                                                                      
[22:11:02] ERROR    OpenLane will now quit.
I'm still very new to this and wondering if anybody can help me figure out how to get past this?
v
Check antenna violations. Hold violations in the design. Check respective reports
d
@cqb The tutorial guides you on fixing hold violations after this error: https://openlane2.readthedocs.io/en/latest/usage/caravel/index.html#id18 …unless you mean that this happens after following those particular steps, which is a bug.
c
I am as a section higher up in the guide, here: https://openlane2.readthedocs.io/en/latest/usage/caravel/index.html#id2 The tutorial walked me through the errors while hardening the aes macro which was successful, but now I am getting them on the user project wrapper. I attempted running the flow with the config changes mentioned in the section you linked and I get this:
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* Antenna
Failed 𐄂
Pin violations: 29
Net violations: 29
Check the report directory of OpenROAD.CheckAntennas.

* LVS
Failed 𐄂
Total Errors: 438
Unmatched Pins: 52
Unmatched Nets: 4
Check the report directory of Netgen.LVS.

* DRC
Failed 𐄂
KLayout DRC errors: 0
Magic DRC errors: 2034
Check the report directories of KLayout.DRC and Magic.DRC.

[20:52:07] ERROR    The following deferred step errors have been encountered:                                            sequential.py:282
[20:52:07] ERROR    2034 Magic DRC errors found.                                                                         sequential.py:284
[20:52:07] ERROR    438 LVS errors found.                                                                                sequential.py:284
[20:52:07] ERROR    OpenLane will now quit.
on my first run for uzer_project_wrapper this was my antenna summary:
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┏━━━━━━━━━━━━━━━━━━┳━━━━━━━━━━┳━━━━━━━━━━┳━━━━━━━━━━━━━━━┳━━━━━━━━━━━━━━━━━━━━┳━━━━━━━┓
┃ Partial/Required ┃ Required ┃ Partial  ┃ Net           ┃ Pin                ┃ Layer ┃
┑━━━━━━━━━━━━━━━━━━╇━━━━━━━━━━╇━━━━━━━━━━╇━━━━━━━━━━━━━━━╇━━━━━━━━━━━━━━━━━━━━╇━━━━━━━┩
β”‚ 10.15            β”‚ 2773.88  β”‚ 28145.14 β”‚ wbs_dat_i[0]  β”‚ mprj/wbs_dat_i[0]  β”‚ met3  β”‚
β”‚ 10.06            β”‚ 2773.88  β”‚ 27916.06 β”‚ wbs_dat_i[1]  β”‚ mprj/wbs_dat_i[1]  β”‚ met3  β”‚
β”‚ 9.97             β”‚ 2773.88  β”‚ 27659.05 β”‚ wbs_adr_i[2]  β”‚ mprj/wbs_adr_i[2]  β”‚ met3  β”‚
β”‚ 9.84             β”‚ 2773.88  β”‚ 27295.37 β”‚ wbs_adr_i[3]  β”‚ mprj/wbs_adr_i[3]  β”‚ met3  β”‚
β”‚ 8.88             β”‚ 2773.88  β”‚ 24624.51 β”‚ wbs_dat_i[8]  β”‚ mprj/wbs_dat_i[8]  β”‚ met3  β”‚
β”‚ 8.81             β”‚ 2773.88  β”‚ 24441.65 β”‚ wbs_cyc_i     β”‚ mprj/wbs_cyc_i     β”‚ met3  β”‚
β”‚ 8.77             β”‚ 2773.88  β”‚ 24332.44 β”‚ wbs_stb_i     β”‚ mprj/wbs_stb_i     β”‚ met3  β”‚
β”‚ 8.77             β”‚ 2773.88  β”‚ 24314.92 β”‚ wbs_dat_i[9]  β”‚ mprj/wbs_dat_i[9]  β”‚ met3  β”‚
β”‚ 8.19             β”‚ 2773.88  β”‚ 22706.79 β”‚ wbs_dat_i[3]  β”‚ mprj/wbs_dat_i[3]  β”‚ met3  β”‚
β”‚ 8.18             β”‚ 2773.88  β”‚ 22689.27 β”‚ wbs_adr_i[4]  β”‚ mprj/wbs_adr_i[4]  β”‚ met3  β”‚
β”‚ 8.13             β”‚ 2773.88  β”‚ 22543.24 β”‚ wbs_adr_i[5]  β”‚ mprj/wbs_adr_i[5]  β”‚ met3  β”‚
β”‚ 8.11             β”‚ 2773.88  β”‚ 22484.83 β”‚ wbs_adr_i[6]  β”‚ mprj/wbs_adr_i[6]  β”‚ met3  β”‚
β”‚ 8.00             β”‚ 2773.88  β”‚ 22188.70 β”‚ wbs_dat_i[17] β”‚ mprj/wbs_dat_i[17] β”‚ met3  β”‚
β”‚ 7.98             β”‚ 2773.88  β”‚ 22134.35 β”‚ wbs_adr_i[7]  β”‚ mprj/wbs_adr_i[7]  β”‚ met3  β”‚
β”‚ 7.91             β”‚ 2773.88  β”‚ 21953.27 β”‚ wbs_adr_i[8]  β”‚ mprj/wbs_adr_i[8]  β”‚ met3  β”‚
β”‚ 7.86             β”‚ 2773.88  β”‚ 21789.71 β”‚ wbs_dat_i[16] β”‚ mprj/wbs_dat_i[16] β”‚ met3  β”‚
β”‚ 7.85             β”‚ 2773.88  β”‚ 21766.35 β”‚ wbs_adr_i[9]  β”‚ mprj/wbs_adr_i[9]  β”‚ met3  β”‚
β”‚ 7.76             β”‚ 2773.88  β”‚ 21516.95 β”‚ wbs_dat_i[10] β”‚ mprj/wbs_dat_i[10] β”‚ met3  β”‚
β”‚ 7.42             β”‚ 2773.88  β”‚ 20588.19 β”‚ wbs_dat_i[25] β”‚ mprj/wbs_dat_i[25] β”‚ met3  β”‚
β”‚ 7.13             β”‚ 2773.88  β”‚ 19768.63 β”‚ wbs_dat_i[15] β”‚ mprj/wbs_dat_i[15] β”‚ met3  β”‚
β”‚ 6.89             β”‚ 2773.88  β”‚ 19104.51 β”‚ wbs_dat_i[4]  β”‚ mprj/wbs_dat_i[4]  β”‚ met3  β”‚
β”‚ 6.84             β”‚ 2773.88  β”‚ 18974.22 β”‚ wbs_dat_i[12] β”‚ mprj/wbs_dat_i[12] β”‚ met3  β”‚
β”‚ 6.82             β”‚ 2773.88  β”‚ 18909.97 β”‚ wbs_dat_i[19] β”‚ mprj/wbs_dat_i[19] β”‚ met3  β”‚
β”‚ 6.78             β”‚ 2773.88  β”‚ 18804.83 β”‚ wbs_dat_i[26] β”‚ mprj/wbs_dat_i[26] β”‚ met3  β”‚
β”‚ 6.65             β”‚ 2773.88  β”‚ 18436.83 β”‚ wbs_dat_i[18] β”‚ mprj/wbs_dat_i[18] β”‚ met3  β”‚
β”‚ 6.46             β”‚ 2773.88  β”‚ 17908.19 β”‚ wbs_dat_i[2]  β”‚ mprj/wbs_dat_i[2]  β”‚ met3  β”‚
β”‚ 6.16             β”‚ 2773.88  β”‚ 17078.73 β”‚ wbs_dat_i[5]  β”‚ mprj/wbs_dat_i[5]  β”‚ met3  β”‚
β”‚ 6.09             β”‚ 2773.88  β”‚ 16883.05 β”‚ wbs_dat_i[24] β”‚ mprj/wbs_dat_i[24] β”‚ met3  β”‚
β”‚ 6.08             β”‚ 2773.88  β”‚ 16856.76 β”‚ wbs_dat_i[6]  β”‚ mprj/wbs_dat_i[6]  β”‚ met3  β”‚
β”‚ 6.00             β”‚ 2773.88  β”‚ 16636.57 β”‚ wbs_dat_i[7]  β”‚ mprj/wbs_dat_i[7]  β”‚ met3  β”‚
β”‚ 5.99             β”‚ 2773.88  β”‚ 16614.35 β”‚ wbs_dat_i[23] β”‚ mprj/wbs_dat_i[23] β”‚ met3  β”‚
β”‚ 5.97             β”‚ 2773.88  β”‚ 16555.94 β”‚ wbs_dat_i[20] β”‚ mprj/wbs_dat_i[20] β”‚ met3  β”‚
β”‚ 5.67             β”‚ 2773.88  β”‚ 15737.02 β”‚ wbs_dat_i[11] β”‚ mprj/wbs_dat_i[11] β”‚ met3  β”‚
β”‚ 5.62             β”‚ 2773.88  β”‚ 15601.34 β”‚ wbs_we_i      β”‚ mprj/wbs_we_i      β”‚ met3  β”‚
β”‚ 5.51             β”‚ 2773.88  β”‚ 15287.24 β”‚ wbs_dat_i[13] β”‚ mprj/wbs_dat_i[13] β”‚ met3  β”‚
β”‚ 5.49             β”‚ 2773.88  β”‚ 15231.75 β”‚ wbs_dat_i[27] β”‚ mprj/wbs_dat_i[27] β”‚ met3  β”‚
β”‚ 5.43             β”‚ 2773.88  β”‚ 15051.81 β”‚ wbs_dat_i[14] β”‚ mprj/wbs_dat_i[14] β”‚ met3  β”‚
β”‚ 5.39             β”‚ 2773.88  β”‚ 14945.52 β”‚ wbs_dat_i[29] β”‚ mprj/wbs_dat_i[29] β”‚ met3  β”‚
β”‚ 5.08             β”‚ 2773.88  β”‚ 14102.60 β”‚ wbs_dat_i[28] β”‚ mprj/wbs_dat_i[28] β”‚ met3  β”‚
β”‚ 4.87             β”‚ 2773.88  β”‚ 13506.79 β”‚ wbs_dat_i[31] β”‚ mprj/wbs_dat_i[31] β”‚ met3  β”‚
β”‚ 4.86             β”‚ 2773.88  β”‚ 13480.51 β”‚ wbs_dat_i[21] β”‚ mprj/wbs_dat_i[21] β”‚ met3  β”‚
β”‚ 4.78             β”‚ 2773.88  β”‚ 13252.70 β”‚ wbs_dat_i[22] β”‚ mprj/wbs_dat_i[22] β”‚ met3  β”‚
β”‚ 4.13             β”‚ 2773.88  β”‚ 11453.59 β”‚ wbs_dat_i[30] β”‚ mprj/wbs_dat_i[30] β”‚ met3  β”‚
β”‚ 2.96             β”‚ 2773.88  β”‚ 8203.11  β”‚ wbs_adr_i[7]  β”‚ mprj/wbs_adr_i[7]  β”‚ met2  β”‚
β”‚ 2.85             β”‚ 2773.88  β”‚ 7897.11  β”‚ wbs_adr_i[5]  β”‚ mprj/wbs_adr_i[5]  β”‚ met2  β”‚
β”‚ 2.83             β”‚ 2773.88  β”‚ 7859.33  β”‚ wbs_adr_i[6]  β”‚ mprj/wbs_adr_i[6]  β”‚ met2  β”‚
β”‚ 2.82             β”‚ 2773.88  β”‚ 7821.56  β”‚ wbs_adr_i[8]  β”‚ mprj/wbs_adr_i[8]  β”‚ met2  β”‚
β”‚ 2.81             β”‚ 2773.88  β”‚ 7783.78  β”‚ wbs_adr_i[9]  β”‚ mprj/wbs_adr_i[9]  β”‚ met2  β”‚
β”‚ 2.79             β”‚ 2773.88  β”‚ 7746.00  β”‚ wbs_dat_i[12] β”‚ mprj/wbs_dat_i[12] β”‚ met2  β”‚
β”‚ 2.78             β”‚ 2773.88  β”‚ 7708.22  β”‚ wbs_dat_i[18] β”‚ mprj/wbs_dat_i[18] β”‚ met2  β”‚
β”‚ 2.76             β”‚ 2773.88  β”‚ 7666.67  β”‚ wbs_dat_i[19] β”‚ mprj/wbs_dat_i[19] β”‚ met2  β”‚
β”‚ 2.75             β”‚ 2773.88  β”‚ 7628.89  β”‚ wbs_dat_i[20] β”‚ mprj/wbs_dat_i[20] β”‚ met2  β”‚
β”‚ 2.74             β”‚ 2773.88  β”‚ 7591.11  β”‚ wbs_dat_i[23] β”‚ mprj/wbs_dat_i[23] β”‚ met2  β”‚
β”‚ 2.71             β”‚ 2773.88  β”‚ 7515.56  β”‚ wbs_dat_i[4]  β”‚ mprj/wbs_dat_i[4]  β”‚ met2  β”‚
β”‚ 2.17             β”‚ 2773.88  β”‚ 6019.56  β”‚ wbs_cyc_i     β”‚ mprj/wbs_cyc_i     β”‚ met2  β”‚
β”‚ 2.05             β”‚ 2773.88  β”‚ 5675.78  β”‚ wbs_dat_i[24] β”‚ mprj/wbs_dat_i[24] β”‚ met2  β”‚
β”‚ 2.03             β”‚ 2773.88  β”‚ 5638.00  β”‚ wbs_dat_i[28] β”‚ mprj/wbs_dat_i[28] β”‚ met2  β”‚
β”‚ 2.02             β”‚ 2773.88  β”‚ 5596.44  β”‚ wbs_dat_i[31] β”‚ mprj/wbs_dat_i[31] β”‚ met2  β”‚
β”‚ 1.91             β”‚ 2773.88  β”‚ 5286.66  β”‚ wbs_we_i      β”‚ mprj/wbs_we_i      β”‚ met2  β”‚
β”‚ 1.79             β”‚ 2773.88  β”‚ 4971.51  β”‚ wb_rst_i      β”‚ mprj/wb_rst_i      β”‚ met3  β”‚
β”‚ 1.27             β”‚ 2773.88  β”‚ 3526.22  β”‚ wbs_adr_i[4]  β”‚ mprj/wbs_adr_i[4]  β”‚ met2  β”‚
β”‚ 1.04             β”‚ 2773.88  β”‚ 2885.52  β”‚ wb_clk_i      β”‚ mprj/wb_clk_i      β”‚ met3  β”‚
β””β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”΄β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”΄β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”΄β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”΄β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”΄β”€β”€β”€β”€β”€β”€β”€β”˜
and stapostpnr from the first run:
c
Yes, that's the section, thanks. I've reran open lane successfully with the modifications described. The manufacturability report looks fine, but the
stapostpnr
summary does not match the example given in the tutorial:
Copy code
┏━━━━━━━━━━┳━━━━━━━━━━┳━━━━━━━━━┳━━━━━━━━━━┳━━━━━━━━━┳━━━━━━━━━━┳
┃          ┃          ┃         ┃          ┃         ┃          ┃
┃          ┃ Hold     ┃ Reg to  ┃          ┃         ┃ of which ┃
┃          ┃ Worst    ┃ Reg     ┃          ┃ Hold    ┃ Reg to   ┃
┃ Corner/… ┃ Slack    ┃ Paths   ┃ Hold TNS ┃ Violat… ┃ Reg      ┃
┑━━━━━━━━━━╇━━━━━━━━━━╇━━━━━━━━━╇━━━━━━━━━━╇━━━━━━━━━╇━━━━━━━━━━╇
β”‚ Overall  β”‚ -0.0061  β”‚ -0.0061 β”‚ -0.0061  β”‚ 3       β”‚ 3        β”‚
β”‚ nom_tt_… β”‚ 0.1391   β”‚ 0.1391  β”‚ 0.0000   β”‚ 0       β”‚ 0        β”‚
β”‚ nom_ss_… β”‚ 0.5329   β”‚ 0.5329  β”‚ 0.0000   β”‚ 0       β”‚ 0        β”‚
β”‚ nom_ff_… β”‚ -0.0045  β”‚ -0.0045 β”‚ -0.0045  β”‚ 1       β”‚ 1        β”‚
β”‚ min_tt_… β”‚ 0.1367   β”‚ 0.1367  β”‚ 0.0000   β”‚ 0       β”‚ 0        β”‚
β”‚ min_ss_… β”‚ 0.5299   β”‚ 0.5299  β”‚ 0.0000   β”‚ 0       β”‚ 0        β”‚
β”‚ min_ff_… β”‚ -0.0061  β”‚ -0.0061 β”‚ -0.0061  β”‚ 1       β”‚ 1        β”‚
β”‚ max_tt_… β”‚ 0.1414   β”‚ 0.1414  β”‚ 0.0000   β”‚ 0       β”‚ 0        β”‚
β”‚ max_ss_… β”‚ 0.5368   β”‚ 0.5368  β”‚ 0.0000   β”‚ 0       β”‚ 0        β”‚
β”‚ max_ff_… β”‚ -0.0029  β”‚ -0.0029 β”‚ -0.0029  β”‚ 1       β”‚ 1        β”‚
└──────────┴──────────┴─────────┴──────────┴─────────┴──────────┴
is this okay? I'm not really sure what I'm looking for in these reports, tbh. Thanks for your guidance and helping me out with this, really appreciate it.
d
@cqb It's normal for there to be some variance in those reports- even small things like placing a cell a few microns away can have a new violations and the PnR tools are highly heuristic. I'll try my best to explain this table, but contributions/corrections from others are welcome. To know a little bit more of what you're supposed to be looking for in these reports, this guide may be helpful: https://openlane2.readthedocs.io/en/latest/usage/corners_and_sta.html tl;dr, you have 1 "hold violation" in 3 "corners" (definitions in the document.) The corners appear to be: β€’ nom_ff_n40C_1v95 β€’ min_ff_n40C_1v95 β€’ max_ff_n40C_1v95 You'll notice "ff" is common to all three. FF indicates here that you "won the silicon lottery" if you ever heard this term- your transistors are very fast. Unfortunately, there is such a thing as too fast, and that means the data changes too quickly at times- causing the hold violation. For most purposes, hold violations indicate a dead chip at those corners. Solving hold violations is not entirely a hard science- you can mess with some variables in OpenLane to maybe achieve timing closure, chiefly in the steps running what's known as "resizing". Here's one such step: https://openlane2.readthedocs.io/en/latest/reference/step_config_vars.html#resizer-timing-optimizations-post-global-routing You'll notice there's a variable called
GRT_RESIZER_HOLD_SLACK_MARGIN
with
0.05
as a default value. Maybe try increasing that to
0.1
for example and run again then see if it's fixed. It's all very trial-and-error.
c
@donn Thanks for all your help! i still haven't figured out how to get rid of the hold violations but I'll spend some time going through the docs to see if I can tinker with some config variables. Really appreciate your guidance!
πŸ™Œ 1