Does anyone have any good references on how much ESD protection is needed when designing your own (digital) I/O pad cells?

You can run simulations against a human body model (HBM) and machine model (MM). A "very robust" ESD design will survive 4000V HBM and 200V MM. Because the ESD circuit is a capacitive load on the pad, ESD is often cut down to a minimum to increase bandwidth at the pad; for that, designers may choose to have a more ESD-sensitive part, with HBM at 2000V or even 1000V.

Thanks