Is there an open source tool that uses gds as input and flags weak power connections?

OpenROAD has power integrity analysis, but that's only for DEF / ODB inputs and digital designs. The other way to do it more generally would be to run parasitic extraction on your design, including the power rails, run a spice simulation, and look at the worst case voltage drop on your power rails. It's feasible for small designs but not for large designs. The other challenge is figuring out what is the worst case input waveform to cause the worst case power draw in your design.

@Austin Rovinski thanks for the reply. Unfortunately, the problem I’m seeing is an sram memory block connected to ground through one narrow li wire and one narrow met2 wire.

I see. Well the nice part about SRAM is that it has a super regular structure. You could potentially simulate just one bit line/word line in spice and draw inferences from that.

Is the problem internal to the ram or how it is connected externally? If the latter you could build a LEF abstract and analyze it in OR

@Matt Liberty thanks for the response. It’s internal to the ram macro - at the connection to the memory array.