@Tim Edwards For a majority of these blocks, we’re dealing with micro amps and mega ohms. Is there really engineering value in requiring post-layout resistance extraction? It may just unnecessarily complicate/slowdown post-layout simulation. A capacitance extraction may be all that’s needed. I may be wrong but what are your thoughts?

You'd have to justify it by running one simulation with capacitance extraction only and one with resistance + capacitance extraction and show that they give essentially the same result. The final set of simulations must be done with an R-C extracted netlist, and I don't think any of the circuits are so large that it's going to take days to simulate, but you can always run quick simulations with only parasitic capacitances during the design phase. Note that most issues with resistance extraction will center around the local interconnect layer; it has a high sheet rho that makes it improper to use for routing; but contacts to local interconnect are not especially good, either, and can have contact resistances in the hundreds of ohms.

Got it, thanks. Watch out for the li layer and contacts.