https://open-source-silicon.dev
Join Slack
is there any documentation on how to get this co-simulation (mixed-signal simulation) going in ngspi...
# analog-design
t
is there any documentation on how to get this co-simulation (mixed-signal simulation) going in ngspice? To date I have been dumping an LVS extracted digital netlist into my schematic but it's not sustainable as it's desperately slow
t
There are multiple ways. See the thread in this channel from December 28. There are some links there to documentation on how to do different types of mixed-signal simulation an co-simulation in ngspice version 42. @Matt Venn also figured out how to do this recently.
✅ 1
m
documentation is scant, but essentially you take your spice, and with ngspice42 you can generate a .so file that you can then use in another spice file
it was extremely easy to run the ngspice demo and didn't take me long to get it to work on my own design
t
Thanks @Matt Venn, I have managed to get something up and running too now. Is there a way of sepcifying the supply voltage as 1V8 without having to manually instantiate the auto_dac and auto_adc primitives and passing in/out_high/low to them?
r
I found this repo quite useful too: https://github.com/Isotel/mixedsim/
m
t
A very tedious debug session earlier this week let me to the conclusion that multiple clocks are not suported. Has anyone else observed this?
@Matt Venn have you tried instantiating a verilator compiled digital design with more than one clock in a spice netlist? as far as i can tell so far it doesn't work.
t
@Tom: Can you post your non-working example?
t
Yes I can. I will have to recreate it though since I removed the need for the second clock in my test so I could make forward progress
m
no I only used one clock
👍 1
11 Views
Open in Slack
PreviousNext
Powered by

What is Linen?

Linen is a search-engine friendly community platform. We offer integrations with existing Slack/Discord communities and make those conversations Google-searchable.

Powered by