@Stefan Schippers there’s a schematic that mixes signal name case. Is it possible to make xschem signal probes case insensitive?

I need to implement an option for that. Xschem is case sensitive because Verilog designs are case sensitive (while Spice and VHDL are not), so I opted for case sensitive node names in xschem.

I’m thinking that it might be a better idea to enforce case sensitivity/insensitivity compatibility by not allowing the same net names with different cases. This would be compatible with verilog, spice and VHDL. If xschem were to only allow one spelling (maybe auto convert case to existing spelling like some IDEs), then there wouldn’t be a problem with probing. Mass copy - paste may be hard to handle though.

@Mitch Bailey makes sense. At the very least I can add some ERC checks, and may be (with user perrmission) autocorrect mixed case net / instance names.