What is the maximum distance from the transistor channels to a tap to substrate? I'm looking at the documentation in the readthedocs site and I can't find anything. It should be a latchup rule, but there is none there. At least, I can't find it.

@Luis Henrique Rodovalho The magic tech file has 15um.

cifmaxwidth ptap_missing 0 bend_illegal \
        "N-diff distance to P-tap must be < 15.0um (LU.2)"
 cifmaxwidth dptap_missing 0 bend_illegal \
        "N-diff distance to P-tap in deep nwell.must be < 15.0um (LU.2.1)"
 cifmaxwidth ntap_missing 0 bend_illegal \
        "P-diff distance to N-tap must be < 15.0um (LU.3)"

The PDK has an obscure reference in the GDS layer definition section for layer 81:14

Low tap density (15um between taps) area. Must be at least 50um from padframe

but I’m wondering if 15um between taps means that any diff should be at most 7um from a tap.

Thanks!