Hi everyone, how would I declare multiple clock nets for OpenLane? We are planning on implementing our own SPI interface, so we need to handle a clock domain crossing.

I found this, but don’t have any actual experience.

This will perform synthesis on more than one clock tree, but it doesn't set up the STA constraints. To set up STA properly with multiple clocks, you will need to write your own custom SDC file that creates two clocks and sets the input/output delays accordingly.

Thanks for the replies. I tried setting

"CLOCK_PORT": ["clk1", "clk2"],

"CLOCK_NETS": ["clk1", "clk2"],

and writing my own SDC file, but the flow is failing Post PnR STA with a seg fault. Has anyone seen experienced this before?

I haven't checked recently but the CLOCK_PORTS couldn't be a list in the past.

Hi, I managed to get multiple clock domains to work. Here are some things that I learned: 1.

CLOCK_NETS

has been deprecated and will not be recognized by OpenLane 2 2. The correct configuration variable to use is

FALLBACK_SDC_FILE

, other sdc file variables have been deprecated 3. To specify a clock domain, use

create_clock

and

set_clock_groups

in the sdc file Thanks to everyone who offered their help!

What has replaced CLOCK_NETS?

I don't think anything replaces CLOCK_NETS. I just removed it from my

config.json

and it runs fine without it.