Just curious, for switched-capacitor designs, to what extent is clock generation the responsibility of the IP designers? Would you be able to obtain a ref clk input or would you have to generate everything internally?

@Tim Edwards (Just so he sees this), Thomas, There is both a PLL and DLL in the current implementation plan although we may settle on PLL only. The Configurable dividers are capable of dividing the PLL/DLL down to ~3Mhz. (48Mhz/16) This is the only tight phase and duty cycle controlled clock available on die. If you (as is likely the case) need something lower than this we should discuss in more detail. It would be better to assume that the ADC/SWCAP blocks are operating with busclock as an input and develop any lower frequency clocks locally. This usually results in the lowest overall "on time" and lowest system energy in real applications.

Assume a clock is available that is the core clock or any divided-down multiple of it. The challenge IP blocks do not include the interface to the CPU (except the programmable filter, which would need to define registers), so any switched cap design can assume that the interface can be designed to handle any clock dividers needed for the IP block's input. The IP block would just need to specify the valid range of input clock frequencies.