I'd recommend adding a frequency range note to the LDO integrated noise spec. 10 Hz to 100 kHz? For circuits receiving a bias current, any thoughts on the expected bias current? Looks like there's some wiggle room with the bias generator spec (0.2-1.0 uA). (EDIT: Source or sink?)

All good questions. I worked out the bias generator values a few days ago and it looks like I failed to update the spec. The final values are 50, 100, 200, 400, and 600 nA. I was assuming that the bias generator sources the current through a pFET and each receiver sinks it through an nFET, and thank you for pointing out that I failed to write down that assumption.

Thanks for clarifying, Tim! Is the idea that each IP block using an ibias will request one of those bias currents (preferably the lowest practical), and the final bias gen IP will be scaled for the values requested?

Yes, that's exactly right.